Multiplexing arrangement

Details Multiplexing arrangement Multiplexing arrangement

1994-02-14

1996-03-12

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

H04J 302

Patent

active

054992630

ABSTRACT:
A circuit is provided for multiplexing data packets, each having sets of n digital words and a residual set of r digital words. The multiplexing arrangement includes an output terminal (OUT), input memory units (RAM0-RAM3) each to receive and to store the data packets in memory portions and each to store n digital words, and a multiplexer (MUX) coupled to the input memory units (RAM0-RAM3) and to transfer the data packets thereof to the output terminal (OUT). The circuit also includes a register (RGN) and a residual register (RGR), each connected in parallel to the input memory units (RAM0-RAM3). The register (RGN) reads and transfers the sets of n digital words to the multiplexer (MUX). The residual register (RGR) reads and transfers the residual set of r digital words to the multiplexer (MUX). The multiplexer (MUX) combines the set of n digital words and the residual set of r digital words, forming a combined set, and providing at least a portion of the combined set to the output terminal (OUT).

REFERENCES:
patent: 4320501 (1982-03-01), Le Dieu et al.
patent: 4593390 (1986-06-01), Hildebrand et al.
patent: 5243600 (1993-09-01), Mori et al.
patent: 5267236 (1993-11-01), Stephenson, Jr.
patent: 5301184 (1994-04-01), Uriu et al.
patent: 5303231 (1994-04-01), Shinomiya et al.
Proceedings International Switching Symposium, vol. 2, 15 Mar. 1987, Phoenix (U.S.) pp. 462-469. M. Becker et al `A protocol and prototype for broadband subscriber access to ISDNs` p. 465, Col. 2, line 19; p. 466, Col. 2, line 32.

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