Multiplexing and demultiplexing system with justification

Details Multiplexing and demultiplexing system with justification Multiplexing and demultiplexing system with justification

1984-11-14

1985-09-17

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

H04J 307

Patent

active

045425000

ABSTRACT:
The multiplexing system comprises a time base (29), a multiplexing unit (31) the output of which is connected to the high rate of delivery connection, synchronization units (25 to 28) which include phase comparing devices and which are connected to the low rate of delivery connections (Ve1 to Ve4), a common justification circuit (32) which delivers the reading clock for the synchronization units (25 to 28), a common circuit of justification authorization (33) the clock input (AJ) of which is connected to the corresponding part of time base (29), of which one governing output is connected to the governing input of the justification circuit (32) and the data output of which is connected to the governing input of a common inserting circuit (34) the data inputs of which are respectively connected to the outputs of the synchronization units (25 to 28) and the outputs (of which are connected) to the inputs of multiplexer (31) which delivers the plesiochronous numerical signals with a high rate of delivery.
The governing input of the common justification authorization circuit (33) is connected to the output of an OR gate (35) the inputs of which are connected to the corresponding outputs (Cph1 to Cph4) of the phase comparing devices in the synchronization units (25 to 28).
In the same manner, the demultiplexing system comprises a common dejustification circuit and a common reading circuit for the justification indications.

REFERENCES:
patent: 4095053 (1978-06-01), Duttweiler et al.
patent: 4132862 (1979-01-01), Ferret et al.
patent: 4196315 (1980-04-01), Boutmy et al.
patent: 4355387 (1982-10-01), Portejoie et al.
patent: 4387459 (1983-06-01), Huffman

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