Multiplexer with short propagation delay and low power...

Details Multiplexer with short propagation delay and low power... Multiplexer with short propagation delay and low power...

1998-12-28

2001-04-03

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

C327S099000, C326S126000

Reexamination Certificate

active

06211721

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to multiplexers of digital signals. More particularly, the invention concerns a digital multiplexer with a short data to output propagation delay and low power consumption.
2. Description of the Related Art
Multiplexers, which are common components of digital logic systems, allow one of a number of inputs to be connected to an output. It is desirable to transmit data from an input of a multiplexer to the output of the multiplexer with as little delay as possible, and with as little power dissipation as possible.
A conventional implementation of a 16:1 multiplexer is to cascade a number of 2:1 multiplexers, as shown in FIG.
1
. Alternatively, other sized multiplexers, for example 4:1 multiplexers, can be cascaded in a similar fashion. In the multiplexer in
FIG. 1
, D
1
, D
2
, . . . D
16
are the data inputs, Y is the output, and S
0
, S
1
, S
2
, and S
3
are the select lines. Because each 2:1 multiplexer adds one gate delay, this circuit requires four gate delays to transmit data from an input to the output. Also, because each 2:1 multiplexer requires a current source, this circuit requires fifteen current sources.
In order to reduce power consumption, and also to reduce the data to output propagation delay, which is the time from when a data input changes state to the time that the output changes state, it is known in the art to construct a multiplexer that does not require a cascade of smaller multiplexers, and in which a single current source is used for all of the inputs. However, the data to output propagation delay for these multiplexers is still too long for many applications. The data to output propagation delay in these multiplexers is too long primarily due to the relatively large amount of capacitance associated with the collector(s) of the input transistors, which is connected to the base of the output transistor.
Consequently, there is a need for a multiplexer with low power consumption and with a reduced data to output propagation delay.
SUMMARY OF THE INVENTION
Broadly, the invention concerns a digital multiplexer that has low power consumption, and a data to output propagation delay of about one gate.
An illustrative embodiment of the multiplexer of the invention comprises a plurality of pairs of emitter coupled input transistors, with each pair comprising a first input transistor and a second input transistor. Pairs of complimentary data inputs are connected to the bases of corresponding pairs of input transistors. The multiplexer also includes a plurality of selection transistors, with the collector of each selection transistor being connected to the emitters of a corresponding pair of input transistors. The emitters of the selection transistors are connected to a main current source. The data at a pair of complimentary data inputs is transmitted to the complimentary outputs by activating the selection transistor connected to the pair of input transistors corresponding with the inputs to be transmitted to the outputs. When a selection transistor is activated, the current source is connected in series with the corresponding pair of input transistors, causing the data at the data inputs at the bases of those input transistors to be transmitted to the complimentary outputs. The power consumption of the multiplexer is low because the single main current source is used for all of the inputs.
In order to reduce the propagation delay between the data inputs and the outputs, cascode transistors are connected between the collectors of the input transistors and the bases of the output transistors. Specifically, the emitter of a first cascode transistor is connected to the collector of each of the first input transistors, and the collector of the first cascode transistor is connected to the base of a first output transistor. Similarly, the emitter of a second cascode transistor is connected to the collector of each of the second input transistors, and the collector of the second cascode transistor is connected to the base of a second output transistor. The cascode transistors isolate the relatively large capacitance associated with the collectors of the first and second input transistors, from the bases of the output transistors, thereby enabling the outputs to switch more quickly, which reduces the data to output propagation delay.
Additionally, bleed current sources are connected to the emitters of the cascode transistors. The bleed currents keep the cascode transistors always “on” in a conducting state, which enables the cascode transistors to switch more quickly, thereby reducing the data to output propagation delay. The currents also keep the voltages at the emitters of the cascode transistors nearly constant regardless of the state of the inputs. Each bleed current source has a current of about 60% of the current of the main current source.
The invention can be implemented in several embodiments. For example, the invention can be implemented with discrete components, or can be implemented in an integrated circuit.
The invention provides the advantages of low power consumption and a short data to output propagation delay of only about one gate. The invention also provides other advantages and benefits, which are apparent from the following description.


REFERENCES:
patent: 3639781 (1972-02-01), Marley
patent: 3838296 (1974-09-01), McLeod
patent: 4486880 (1984-12-01), Jeffrey et al.
patent: 4628216 (1986-12-01), Mazumder
patent: 4905238 (1990-02-01), Rinaldis
patent: 5075574 (1991-12-01), Boudon
patent: 5210450 (1993-05-01), Parkinson
patent: 5801571 (1998-09-01), Allen et al.

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