Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2006-03-28
2006-03-28
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
Reexamination Certificate
active
07019679
ABSTRACT:
A differential multiplexer includes a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes first, second, third and fourth transistors. The first and second transistors input the positive input signal. The third and fourth transistors input the negative input signal. Outputs of the first and third transistors are connected to the positive output signal. Outputs of the second and fourth transistors are connected to the negative output signal. The positive and negative output signals are controlled using gate voltages on the first and fourth transistors. The second and third transistors are turned off when the differential multiplexer is in use. The transistors are cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals.
REFERENCES:
patent: 4190805 (1980-02-01), Bingham
patent: 4978957 (1990-12-01), Hotta et al.
patent: 4989003 (1991-01-01), Sauer
patent: 5130572 (1992-07-01), Stitt et al.
patent: 5191336 (1993-03-01), Stephenson
patent: 5973632 (1999-10-01), Tai
patent: 6037891 (2000-03-01), Griph
patent: 6252454 (2001-06-01), Thompson et al.
patent: 6259745 (2001-07-01), Chan
patent: 6362697 (2002-03-01), Pulvirenti
patent: 6373343 (2002-04-01), Baldwin et al.
patent: 6489913 (2002-12-01), Hansen et al.
patent: 6531973 (2003-03-01), Brooks et al.
patent: 6573853 (2003-06-01), Mulder
patent: 6614375 (2003-09-01), Hochschild
patent: 6674388 (2004-01-01), Mulder
patent: 6788238 (2004-09-01), Mulder
patent: 2004/0257255 (2004-12-01), Mulder
Abo, A.M. and Gray, P.R., “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,”IEEE Journal of Solid-State Circuits, IEEE, vol. 34, No. 5, May 1999, pp. 599-606.
Brandt, B.P. and Lutsky, J., “A 75-mW, 10-b, 20-MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist,”IEEE Journal of Solid-State Circuits, IEEE, vol. 34, No. 12, Dec. 1999, pp. 1788-1795.
Bult, Klaas and Buchwald, Aaron, “An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,”IEEE Journal of Solid-State Circuits, IEEE, vol. 32, No. 12, Dec. 1997, pp. 1887-1895.
Cho, T.B. and Gray, P.R., “A 10 b, 20 Msamples/s, 35 nW Pipeline A/D Converter,”IEEE Journal of Solid-State Circuits, IEEE, vol. 30, No. 3, Mar. 1995, pp. 166-172.
Choe, M-J. et al., “A 13-b 40-Msamples/s CMOS Pipelined Folding ADC with Background Offset Trimming,”IEEE Journal of Solid-State Circuits, IEEE, vol. 35, No. 12, Dec. 2000, pp. 1781-1790.
Choi, M. and Abidi, A., “A 6-b 1.3-Gsample/s A/D Converter in 0.35-μm CMOS,”IEEE Journal of Solid-State Circuits, IEEE, vol. 36, No. 12, Dec. 2001, pp. 1847-1858.
Flynn, M. and Sheahan, B., “A 400-Msample/s, 6-b CMOS Folding and Interpolating ADC,”IEEE Journal of Solid-State Circuits, IEEE, vol. 33, No. 12, Dec. 1998, pp. 1932-1938.
Geelen, G., “A 6b 1.1GSample/s CMOS A/D Converter,”IEEE International Solid-State Circuits Conference, IEEE, 2001, pp. 128-129 and 438, no month given.
Hoogzaad, G. and Roovers, R., “A 65-mW, 10-bit, 40-Msample/s BiCMOS Nyquist ADC in 0.8 mm2,”IEEE Journal of Solid-State Circuits, IEEE, vol. 34, No. 12, Dec. 1999, pp. 1796-1802.
Hosotani, S. et al., “An 8-bit 20-MS/s CMOS A/D Converter with 50-mW Power Consumption,”IEEE Journal of Solid-State Circuits, IEEE, vol. 25, No. 1 Feb. 1990, pp. 167-172.
Ingino, J.M. and Wooley, B.A., “A Continuously Calibrated 12-b, 10-MS/s, 3.3-V A/D Converter,”IEEE Journal of Solid-State Circuits, IEEE, vol. 33, No. 12, Dec. 1998, pp. 1920-1931.
Ito, M. et al., “A 10 bit 20 MS/s 3 V Supply CMOS A/D Converter,”IEEE Journal of Solid-State Circuits, IEEE, vol. 29, No. 12, Dec. 1994, pp. 1531-1536.
Kattman, K. and Barrow, J., “A Technique for Reducing Differential Non-Linearity Errors in Flash A/D Converters,”IEEE International Solid-State Conference, IEEE, 1991, pp. 170-171, no month given.
Kusumoto, K. et al., “A 10-b 20-MHz 30-mW Pipelined Interpolating CMOS ADC,”IEEE Journal of Solid-State Circuits, IEEE, vol. 28, No. 12, Dec. 1993, pp. 1200-1206.
Lewis, S. et al., “A 10-b 20-Msamples/s Analog-to-Digital Converter,”IEEE Journal of Solid-State Circuits, IEEE, vol. 27, No. 3, Mar. 1992, pp. 351-358.
Mehr, I. and Singer, L., “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,”IEEE Journal of Solid-State Circuits, IEEE, vol. 35, No. 3, Mar. 2000, pp. 318-325.
Nagaraj, K. et al., “Efficient 6-Bit A/D Converter Using a 1-Bit Folding Front End,”IEEE Journal of Solid-State Circuits, IEEE, vol. 34, No. 8, Aug. 1999, pp. 1056-1062.
Nagaraj, K. et al., “A Dual-Mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D Converter in a 0.25-μm Digital CMOS,”IEEE Journal of Solid-State Circuits, IEEE, vol. 35, No. 12, Dec. 2000, pp. 1760-1768.
Nauta, B. and Venes, A., “A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter,”IEEE Journal of Solid-State Circuits, IEEE, vol. 30, No. 12, Dec. 1995, pp. 1302-1308.
Pan, H. et al., “A 3.3-V 12-b 50-MS/s A/D Converter in 0.6-μm CMOS with over 80-dB SFDR,”IEEE Journal of Solid-State Circuits, IEEE, vol. 35, No. 12, Dec. 2000, pp. 1769-1780.
Song, W-C. et al., “A 10-b 20-Msample/s Low-Power CMOS ADC,”IEEE Journal of Solid-State Circuits, IEEE, vol. 30, No. 5, May 1995, pp. 514-521.
Sumanen, L. et al., “A 10-bit 2000-MS/s CMOS Parallel Pipeline A/D Converter,”IEEE Journal of Solid-State Circuits, IEEE, vol. 36, No. 7, Jul. 2001, pp. 1048-1055.
Taft, R.C. and Tursi, M.R., “A 100-MS/s 8-b CMOS Subranging ADC with Sustained Parametric Performance from 3.8 V Down to 2.2 V,”IEEE Journal of Solid-State Circuits, IEEE, vol. 36, No. 3, Mar. 2001, pp. 331-338.
van der Ploeg, H. and Remmers, R., “A 3.3-V, 10-b 25-Msample/s Two-Step ADC in 0.35-μm CMOS,”IEEE Journal of Solid-State Circuits, IEEE, vol. 34, No. 12, Dec. 1999, pp. 1803-1811.
van der Ploeg, H. et al., “A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2With Mixed-Signal Chopping and Calibration,”IEEE Journal of Solid-State Circuits, IEEE, vol. 36, No. 12, Dec. 2001, pp. 1859-1867.
Vorenkamp, P. and Roovers, R., “A 12-b, 60-Msample/s Cascaded Folding and Interpolating ADC,”IEEE Journal of Solid-State Circuits, IEEE, vol. 32, No. 12, Dec. 1997, pp. 1876-1886.
Wang, Y-T. and Razavi, B., “An 8-bit 150-MHz CMOS A/D Converter,”IEEE Journal of Solid-State Circuits, IEEE, vol. 35, No. 3, Mar. 2000, pp. 308-317.
Yotsuyanagi, M. et al., “A 2 V, 10 b, 20 Msamples/s, Mixed-Mode Subranging CMOS A/D Converter,”IEEE Journal of Solid-State Circuits, IEEE, vol. 30, No. 12, Dec. 1995, pp. 1533-1537.
Yu, P.C. and Lee, H-S., “A 2.5-V, 12-b, 5-Msample/s Pipelined CMOS ADC,”IEEE Journal of Solid-State Circuits, IEEE, vol. 31, No. 12, Dec. 1996, pp. 1854-1861.
Miyazaki et al., ISSCC 2002/Session 10/High-Speed ADCs/10.5, “A 16mW 30 MSample/s 10b Pipelined A/D Converter using a Pseudo-Differential Architecture”, Feb. 5, 2002, 3 pgs.
Sushihara et al., ISSCC 2002/Session 10/High-Speed ADCs/10.3, “A 7b 450 MSample/s 50mW CMOS ADC in 0.3 mm2”, Feb. 5, 2002, 3 pgs.
Dingwall et al., IEEE Journal of Solid-State Circuits, vol. SC-20 No. 6, “An 8-MHz CMOS Subranging 8-Bit A/D Converter”, Dec. 1985, pp. 1138-1143.
Mulder Jan
van der Goes Franciscus Maria Leonardus
Broadcom Corporation
Sterne Kessler Goldstein & Fox P.L.L.C.
Young Brian
LandOfFree
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