Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
2000-09-05
2004-07-06
Pham, Chi (Department: 2663)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C327S407000
Reexamination Certificate
active
06760349
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to multiplexers for use in switching apparatus for communication networks. More specifically, the invention pertains to a high speed, low power consumption, multiplexer, or MUX, including a plurality of inputs and means to route an incoming electrical signal to a single output. The MUX has a circuit topology which includes groupings, or sections, of a plurality of individual multiplexer channels, controlled by selectively actuated current sources. The outputs of the channels within each channel section are connected in parallel relation, feeding a respective pair of common-base amplifiers. The outputs of these common-base amplifiers, in turn, are connected in parallel, to provide a single output channel.
2. Description of the Prior Art
Multiplexers are commonly used in a crosspoint switch device to route data signals from any of a plurality of selected input ports to a selected output port, or to a selected plurality of output ports. The typical circuit topology uses a plurality of 2 to 1 or 4 to 1 multiplexers, of a sufficient number to provide the desired total number of inputs. Thus, for example, a MUX array having 60 inputs and 1 output would include a first bank of fifteen, 4 to 1 input multiplexers. This would provide the required total of 60 input ports. The fifteen outputs of the bank of input multiplexers are then fed to the inputs of a second bank of four, 4 to 1 intermediate multiplexers. The last input of the fourth intermediate multiplexer is unused. Finally, the four outputs of the bank of intermediate multiplexers are fed to the inputs of a single, 4 to 1 output multiplexer, having one output channel. To expand this basic MUX array to provide a crosspoint switch with 60 input channels and 60 output channels, sixty of these MUX arrays would be required. The respective inputs of these arrays would be connected in parallel, and their outputs would remain discrete. Even the relatively simple, 60 to 1 MUX array just described uses a total of twenty individual multiplexers. One consequence of this traditional design is high power consumption, as the control circuitry for actuating individual channels within each bank of multiplexers requires relatively high voltages to operate, typically 3.3 volts. The conventional channel selection circuit uses a differential pair of switching transistors. These transistors redirect the output of a single current source within each multiplexer bank to the proper circuit channel. With this arrangement, every time the number of input channels is doubled, a higher supply voltage must be used. If the supply voltage could be reduced, it would result in lower power consumption and less heat dissipated by the MUX.
It should also be noted that the three stage design results in more signal jitter, or time-based waveform distortion, as each signal must be routed through three multiplexers in passing from the input to the output. Of course, any distortion of the signal waveform as consequence of passing through a multiplexer is undesirable.
Consequently, the need exists for a multiplexer which reduces the number of circuit channels which must be instantaneously operative to route a signal.
The need also exists for a multiplexer which maintains high speed operation yet provides a reduction in the overall power consumed by the multiplexer.
The need also exists for a multiplexer using a circuit topology with reduced parasitic capacitance, to provide an increase in operational speed for a given size of a multiplexer, or to maintain the same operational speed with an increase in the size of the multiplexer.
The need also exists for a multiplexer exhibiting reduced signal jitter over prior art designs, for a given size of the multiplexer.
SUMMARY OF THE INVENTION
The multiplexer, or MUX, of the present invention is comprised of a plurality of discrete, independently powered, channel sections. Each channel section, in turn, includes a plurality of individual channels, each preferably having an input buffer amplifier and an output Ft-doubler amplifier. Differential circuitry is used for both the buffer and the doubler amplifiers.
The components of each channel are powered by switchable bias current sources which are selectively actuated by a decoder. Only the current sources for the channel selected to route the signal are activated at any given moment. Thus, the channels which are not in use for routing a signal are biased off to save power and reduce dissipated heat.
The differential outputs of the channels within each channel section are connected in parallel, and fed to a pair of common-base amplifiers. Bleeder current sources are connected to the emitters of the common-base amplifiers to stabilize the quiescent state of the amplifiers. This effectively reduces signal jitter for the data passing through the multiplexer, and increases the speed performance of the multiplexer.
The outputs of common-base amplifiers of each channel section are connected in parallel, and may optionally be wired to the inputs of a pair of emitter follower amplifiers, for additional gain through the multiplexer. The outputs of the emitter follower amplifiers then constitute the outputs of the multiplexer.
The ratio of the number of common-base amplifiers to the number of channels within each channel section bears a predetermined relationship. This ratio affects the speed performance of the multiplexer. If the ratio is too low, say 1 to 60 (0.0167), the array will be unacceptably slow in signal routing operations. If the ratio is higher, on the order 6 to 10 (0.60), the speed of the multiplexer will be perfectly acceptable. Ratios between these upper and lower ratios may be acceptable or unacceptable, depending upon the particular application.
Arranging the channels into groups or sections reduces the parasitic capacitance which would otherwise result from a single, large scale parallel connection arrangement of the channel outputs. The lowered parasitic capacitance allows higher speed operation for a given array size.
Using individual current sources to power each individual channel reduces the consumption of power in two ways. First, only one current source is activated at a time to select the desired input channel. Thus, irrespective of the size of the MUX, only one bias current is activated at any moment when a signal is routed. Second, a lower voltage may be used to power the channels, as the prior art differential switch is replaced with a decoder, which only turns on the current source for the selected channel. Using this arrangement, the operating voltage is reduced and it does not need to be increased for a multiplexer with a larger number of inputs.
These and other objects and features of the present invention will become apparent in the detailed description and the accompanying drawings to follow.
REFERENCES:
patent: 6211721 (2001-04-01), Smetana
patent: 6239646 (2001-05-01), Navabi et al.
patent: 6385214 (2002-05-01), Kikuchi et al.
Flower Graham M.
Ho Peter
Walker Richard C.
Ferris Derrick W
Pham Chi
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