Multiplexer frame synchronization technique

Multiplex communications – Wide area network – Packet switching

Patent

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Details

3701051, 375116, H04J 306

Patent

active

049301250

ABSTRACT:
Methods for quickly determining loss of synchronization and for quickly reestablishing synchronization of a sub-aggregate frame having primary and secondary frames and contained within an independently synchronized aggregate are provided. In determining loss of synchronization, synch bits are located in the secondary frame such that when the composite subaggregate frame is synchronized the synch bits are chosen to be inserted into the same predetermined position in the aggregate. The synch bits are provided with values such that a collection of synch bits of a composite frame provides an internally non-repeating pattern. By comparing bit values received in the predetermined location of the aggregate at the synch bit rate with the non-repeating pattern, a determination is made as to whether synchronization has been lost. To reestablish synchronization, during data receipt, the bits located in the predetermined synch bit location in the aggregate frame are sequentially inserted into a number of buffers, the number being equal to the frame rate of the subaggregate divided by the synch rate of the synch bits. Then, upon loss of synchronization, a local pointer value is stored upon receipt of a synch bit candidate, the bit patterns in the buffers are scanned to find the buffer containing the internally non-repeating synch pattern, and a pointer correction indication is determined by comparing the local pointer value to a system pointer value dictated by the buffer found to contain the synch bits, and the phase of the internally non-repeating synch pattern in that buffer.

REFERENCES:
patent: 4107608 (1978-08-01), Saburi
patent: 4740962 (1988-04-01), Kish, III
patent: 4764921 (1988-08-01), Graves et al.
patent: 4811367 (1989-03-01), Tajika
patent: 4847877 (1989-07-01), Besseyre

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