Multiplexer for multiplexing insertion codes and a digital data

Details Multiplexer for multiplexing insertion codes and a digital data Multiplexer for multiplexing insertion codes and a digital data

1987-07-20

1989-06-06

Griffin, Robert L.

Multiplex communications

Wide area network

Packet switching

307243, 328104, H04J 304

Patent

active

048377635

ABSTRACT:
A multiplexer includes first and second frequency dividers and first and second selectors. The first frequency divider receives a clock signal which determines a multiplexing time slot and outputs a first signal every M (M.gtoreq.2) time slots. The second frequency divider receives the first signal from said first frequency divider and outputs N (N.gtoreq.1) second signals having different phases. The first selector converts N insertion codes such as a frame synchronization code and a service code into one code signal train on the basis of the second signals. The second selector receives a digital data signal train having an alternate repetition of a digital data signal using (M-1) continuous time slots and a gap of one time slot and inserts the insertion codes of the code signal train on the basis of the first signal.

REFERENCES:
patent: 3676684 (1972-07-01), De Lange
patent: 4182988 (1980-01-01), Murakami
patent: 4381560 (1983-04-01), Farrow
patent: 4485478 (1984-11-01), Takada

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