Multiplexer for an ATM network which employs a hierarchical cell

Details Multiplexer for an ATM network which employs a hierarchical cell Multiplexer for an ATM network which employs a hierarchical cell

1996-10-25

1999-01-26

Pham, Chi H.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370415, H04L 1254

Patent

active

058645560

ABSTRACT:
A multiplexer for use in conjunction with a cell-based network, which includes a plurality of access terminals each of which receives respective cells, each of the cells having one of a plurality of different classifications, a plurality of FIFO buffers each of which is coupled to a respective one of the access terminals for queuing the cells received at the respective access terminals, a plurality of decoding elements each of which is coupled to a respective one of the FIFO buffers, and, an allocation circuit which generates a coded selection signal that is applied to each of the decoding elements, wherein the decoding elements each decode the coded selection signal for selectively reading the cells out of the FIFO buffers in a manner whereby the cells are read out of the FIFO buffers in an order which is dependent upon their classification. In the disclosed embodiment, the allocation circuit includes a memory which stores indexed connection time and date data at addressable storage locations in the memory, wherein the connection time and date data is stored in a hierarchical fashion according to respective connection priority levels, and is organized in different blocks each comprised of groups of connections having the same priority level, an addressing circuit which cycles through the memory addresses in such a manner that the connection time and date data of the highest priority level group is read out first and the connection time and date data of the lowest priority level group is read out last, a current date generating circuit which generates a current date at an allocation circuit cycle rate, a comparison circuit which compares the data and time of a currently addressed connection with the current date and which issues a validation signal upon detecting a match, and, a selector circuit which generates the coded selection signal in response to the validation signal.

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