Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Patent
1997-02-25
2000-07-18
Pham, Chi H.
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
370210, G06F 1710
Patent
active
060920939
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a frequency multiplexer for combining n single signals of bandwidth (B), sampled with a sampling frequency (fa
), which are subjected to a Fourier transform to obtain complex input signals, which are each weighted and fed to a chain of delay and addition elements. It also relates to a frequency demultiplexer for frequency separation of a frequency multiplexer signal, composed of n single signals of bandwidth (B) sampled at the sampling frequency (fa) based on this type of frequency multiplexer structure.
Such demultiplexer/multiplexers are known, for instance from German Patent DE 41 16 495 C1. Such frequency demultiplexer/multiplexers find manifold uses, for instance in satellite communications technology. There it is especially urgently necessary that the volume, weight and power consumption be kept low.
SUMMARY OF THE INVENTION
For the present invention as well, it is therefore an object to provide a frequency demultiplexer/multiplexer of the type referred to at the outset that while fully performing the requisite operating functions makes do with the least possible expense, for instance with minimal chip area and/or the lowest possible power consumption.
According to the invention the frequency multiplexer device for combining a plurality (n) of single signals of bandwidth (B), sampled with a sampling frequency (fa
), includes means for performing a Fourier transformation of the single signals to obtain complex input signals each having an imaginary portion and a real portion and a plurality of devices for generating an output signal for multiplexing from the imaginary portion and the real portion of each complex input signal. Each device for generating the output signal includes respective different chains of serially connected delay elements for delaying the real and imaginary portion to form differently delayed real and imaginary signal portions and means for combining and weighting pairs of differently delayed real and imaginary signal portions to be weighted with an identical one of a number of different weighting factors to form respective weighted combined signals for each different weighting factor, each of the means for combining and weighting comprising a series circuit branch including an adder and a single multiplier connected to the adder arranged to receive an addition result from the adder, the single multiplier comprising means for weighting the addition result of the adder with one of the weighting factors; and means for combining resultant signals from the multipliers to obtain the output signal.
In various preferred embodiments of the invention the frequency multiplexer also includes means for quantization of imaginary and real portions of the complex input signals, means for generating a correction signal for mean quantization errors and means for feeding the correction signal into one of the series circuit branches between its adder and single multiplier.
Furthermore features of the invention and preferred embodiments are described in the appended detailed description and claimed in the appended claims.
The frequency demultiplexer/multiplexer according to the invention has the advantages that at minimal expense for chip area and also with minimal power consumption, it is capable of meeting all the required operating functions. These advantages gain still further significance for a demultiplexer of HMM structure with many identical HMM cells, where it is possible to economize on a few multipliers or status memories in each cell and the structure of the status memories is also modified such that they consume less energy. Further advantages arise because some identical component groups are utilized multiple times in time-division multiplexing. Moreover, by restructuring addition and multiplication arrays into more-simple multiplication and addition trees, the possibility is gained that the typical word width shortening by quantizing downstream of multiplication stages, with the attendant quant
REFERENCES:
patent: 5587939 (1996-12-01), Soleymani et al.
Bayha Erwin
Goeckler Heinz
Pham Chi H.
Robert & Bosch GmbH
Striker Michael J.
Tran Maiknanh
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