Multiplexer/demultiplexer circuitry for LSI implementation

Details Multiplexer/demultiplexer circuitry for LSI implementation Multiplexer/demultiplexer circuitry for LSI implementation

1987-09-28

1989-05-30

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 86, 370100, 370106, H04J 306

Patent

active

048357707

ABSTRACT:
A multiplexer/demultiplexer comprises a code pattern generator for generating a series of unique code patterns at periodic intervals, a plurality of multiplexers cascaded from the code pattern generator to one end of a channel. Each of the multiplexers includes a synchronizer for detecting a particular one of the unique code patterns and a slot selector for multiplexing input data packets into time slots uniquely identified by the particular code pattern to form a data bit stream with the code patterns which is forwarded to the channel. A plurality of demultiplexers are connected to the opposite end of the channel, each of the demultiplexers comprising a synchronizer for detecting a particular one of the code patterns from the data bit stream and a gate for extracting data packets from the time slots uniquely identified by the detected code pattern.

REFERENCES:
patent: 4482999 (1984-11-01), Janson et al.
patent: 4594708 (1986-06-01), Servel et al.
patent: 4727542 (1988-02-01), Rokugo et al.

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