Multiplexer control scheme

Details Multiplexer control scheme Multiplexer control scheme

1999-01-15

2001-03-27

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

C327S407000

Reexamination Certificate

active

06208193

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to multiplexers generally and, more particularly, to a circuit and a method for implementing a multi-input multiplexer using Current Mode Logic (CML) or other swing logic.
BACKGROUND OF THE INVENTION
FIG. 1
a
illustrates a circuit
10
illustrating a conventional approach to implementing a multiplexer. The circuit
10
comprises a multiplexer
11
and a decoder
12
. The multiplexer
11
presents a first signal (i.e., a) or a second signal (i.e., b) in response to a control signal generated by the decoder
12
. The decoder
12
may generate the control signal in response to the select signal (i.e., SELO).
FIG. 1
b
shows a more detailed diagram of the multiplexer
11
. The multiplexer
11
comprises a number of stages
13
a
-
13
n.
The stage
13
a
comprises a number of transistor pairs
14
a
-
14
b
and the stage
13
n
comprises a number of transistor pairs
16
a
-
16
b.
Each of the transistor pairs receives a differential input signal (e.g., A and An or B and Bn, respectively). A number of select transistors
18
a
-
18
n
respond to a number of control signals (i.e., SEL_A and SEL_B) generated by the decoder
12
. An example of the circuit
10
may be found in copending application, U.S. Ser. No. 09/182,556, filed on Oct. 19, 1998, entitled HIGH-SPEED, MULTIPLE-INPUT MULTIPLEXER SCHEME, which is hereby incorporated by reference in its entirety. The circuit
10
comprises N single ended select lines that are used for an N-input multiplexer. Only one select line is selected at a given time. This activates the selected stage
13
a
-
13
n
while the non-selected stages are de-activated.
The circuit
10
is particularly useful for applications that have CML-type inputs and CML-type outputs. However, the circuit
10
may not be as useful where large output swings are required. For example, where the output swings higher than standard CML levels (e.g., 400 mV), the base collector may start leaking, and, in the extreme case, even forward bias. An additional limitation occurs when the input to the multiplexer
11
runs across two different power supplies. This means that potentially Vcb=Vswing+power supply drop (e.g., 0.4 v+0.2 v=0.6 v). Again, the base to collector junction could be forward biased.
Some of the disadvantages of the circuit
10
can be solved by adding an emitter follower on the input. However, such an approach generally requires three-level gating, which may not be practical for 3.3V supplies.
Referring to
FIG. 2
a,
a circuit
50
is shown that can be used for instances where large output swings are required or an interface between two power supply zones is required. The circuit
50
generally comprises a multiplexer
52
, a decoder
54
and a boost circuit
56
. The multiplexer
52
is similar to the circuit
10
. The boost circuit
56
may comprise a transistor
58
, a transistor
60
, a transistor
62
, a transistor
64
and a number of current sources
66
a
-
66
n.
A CML multiplexer can be used to do the functional selects followed by a swing boost circuit which contains an emitter follower (level shift) to keep the Vbc on the differential pair from forward biasing.
The circuit
50
has limitations associated with current, layout, stage distortion, noise induced distortion, matching, delay, and output swing variability. The additional circuitry generally increases the overall current use. The additional circuitry also generally increases the layout of the circuit
50
and increases distortion. Noise induced distortion can be caused if an additional buffer is far enough from the multiplexer
52
. Power supply noise could be an issue it both buffers do not experience identical noise environment. This could result in noise induced distortion when matching two data paths (such as in an output buffer application where a pump up signal is matched to a pump down signal) . The circuit
50
requires matching two buffers to two other buffers. The two stages will have a larger delay than desired. Output swing variability is difficult to achieve in the output level swing of the circuit
50
(or the circuit
10
).
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a plurality of input devices, a plurality of de-select devices and a selector device. The plurality of input devices may each be configured to receive an input signal. The plurality of de-select devices may each be configured to present an output in response (i) one of the plurality of inputs and (ii) one of a plurality of de-select signals. The selector device may be configured to present the plurality of de-select signals. In general, all but one of the de-select signals is active at a time.
The objects, features and advantages of the present invention include providing a multiplexer that may have reduced (i) current, (ii) layout, (iii) stage distortion, (iv) noise induced distortion, (v) matching delay, and (vi) output swing variability.


REFERENCES:
patent: 4572967 (1986-02-01), Metz
patent: 4932027 (1990-06-01), Scharrer
patent: 5289048 (1994-02-01), Ishhara et al.
patent: 5352987 (1994-10-01), Harvey
patent: 5402013 (1995-03-01), Friedrich

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