Multiplexer circuit

Details Multiplexer circuit Multiplexer circuit

2007-11-20

2010-10-19

Nguyen, Hai L (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

C327S408000

Reexamination Certificate

active

07816972

ABSTRACT:
Disclosed herein is a multiplexer circuit. The multiplexer circuit includes a first differential output unit, a second differential output unit, and a selection unit. The first differential output unit receives NRZ input signals (D1andD1) and a clock signal (CLK), and generates differential RZ-mode outputs (R1andR1). The second differential output unit receives NRZ input signals (D2andD2) and an inverted clock signal (CLK), and generates differential RZ-mode outputs (R2andR2). The selection unit receives the RZ-mode output signals (R1,R1, R2, andR2) generated at the first differential output unit and the second differential output unit, and generates NRZ mode outputs in each half cycle of the clock signal (CLK).

REFERENCES:
patent: 6310509 (2001-10-01), Davenport et al.
patent: 6614291 (2003-09-01), Zhao et al.
patent: 7123074 (2006-10-01), Neumann
patent: 7319356 (2008-01-01), Karim

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