Multiplexer and priority control method for packet data...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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C370S394000, C370S538000

Reexamination Certificate

active

07035265

ABSTRACT:
Opportunities to transmit ATM cells of identical level onto an ATM line are equally afforded to respective terminal side lines. In a cell assembler/disassembler, data from the terminal side lines1100are turned into ATM cells, and the ATM cells are assigned priority levels. Then, the ATM cells are stored in internal buffers111–116respectively corresponding to the terminal side lines1100. The priority controller1210selects the ATM cells of the highest priority levels from within the respective internal buffers, and further selects the ATM cell of the highest priority level as an ATM cell to-be-transmitted from among the selected ATM cells. In the presence of a plurality of such ATM cells of the highest priority level, the priority controller1210determines the ATM cell to-be-transmitted in accordance with the priority sequence of the internal buffers in which the ATM cells of the highest priority level are stored. Each time the priority controller1210selects the ATM cell to-be-transmitted, it alters the priority sequence of the internal buffers so that the priority sequence of the internal buffer having stored the ATM cell to-be-transmitted therein may become the latest.

REFERENCES:
patent: 5499238 (1996-03-01), Shon
patent: 5805595 (1998-09-01), Sharper et al.

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