Multiplexed wide interface to SGRAM on a graphics controller for

Details Multiplexed wide interface to SGRAM on a graphics controller for Multiplexed wide interface to SGRAM on a graphics controller for

1997-05-05

1999-05-04

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Interface

345515, 345516, 345519, 345523, 345524, 345525, 36523003, G06F 1316

Patent

active

059008873

ABSTRACT:
A graphics controller chip has an integrated graphics memory. A wide data interface is provided to a RAM array storing graphics pixel data in the graphics memory. The wide data interface provides 256 bits of data during normal writes, but in a block-write mode the wide data interface is split into two sections. One section contains 128 bits of data, while a second section contains 128 mask bits. The data is replicated to eight half-width columns in the RAM array, while the mask bits disable writing some of the data to the RAM. Separate byte-mask bits can be provided for disabling bytes during normal mode writes, but these byte-mask bits cause multiple copies of the data to be disabled. Thus the mask bits in the second section are more useful as they can disable any individual byte in any of the eight columns. A block write of 64 2-byte pixels can be performed in a single step, as no color-data register and no mask register is needed. The 128 bits of data provide an 8-pixel data pattern which is copied to eight columns. The 8-pixel data pattern provides a complex 8-color pattern for background fills behind foreground graphics data.

REFERENCES:
patent: 4620186 (1986-10-01), Krause et al.
patent: 5142637 (1992-08-01), Harlin et al.
patent: 5282177 (1994-01-01), McLaury
patent: 5315560 (1994-05-01), Nishimoto et al.
patent: 5319606 (1994-06-01), Bowen et al.
patent: 5323346 (1994-06-01), Takahashi
patent: 5381376 (1995-01-01), Kim et al.
patent: 5394172 (1995-02-01), McLaury
patent: 5394535 (1995-02-01), Ohuchi
patent: 5473566 (1995-12-01), Rao
patent: 5473573 (1995-12-01), Rao
patent: 5497352 (1996-03-01), Magome
patent: 5506814 (1996-04-01), Hush et al.
patent: 5511025 (1996-04-01), Smith et al.
patent: 5553252 (1996-09-01), Takayanagi et al.
patent: 5764963 (1998-06-01), Ware et al.
patent: 5781496 (1998-07-01), Pinkham et al.
patent: 5787046 (1998-07-01), Furuyama et al.
patent: 5802006 (1998-09-01), Ohta
Micron MT41LC256K32D4 Synchronous Graphics RAM datasheet, Micron Technology, 1995 UPD481850 Synchronous GRAM datasheet, NEC Corp., Dec. 6, 1994.

Affiliated with

Also associated with

Rating

Multiplexed wide interface to SGRAM on a graphics controller for does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiplexed wide interface to SGRAM on a graphics controller for, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiplexed wide interface to SGRAM on a graphics controller for will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1872993