Multiplexed synchronous/asynchronous data bus

Details Multiplexed synchronous/asynchronous data bus Multiplexed synchronous/asynchronous data bus

1989-01-27

1990-11-20

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375 36, 455 73, 455 88, 455 78, 370 5, 370 84, 370 31, H04B 138, H04L 516

Patent

active

049724320

ABSTRACT:
A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when another of the bus lines is held in a logic high state.

REFERENCES:
patent: 4369516 (1983-01-01), Byrns
patent: 4380060 (1983-04-01), Wilhelm
patent: 4593155 (1986-06-01), Hawkins
patent: 4667191 (1987-05-01), Comroe et al.
patent: 4680787 (1987-07-01), Marry
patent: 4725836 (1988-02-01), Guidos
patent: 4742560 (1988-05-01), Arai
"Interface Between Data Terminal Equipment and Data Communication Equipment Employing Serial Binary Data Interchange", EIA Standard RS-232-C, Revision of RS-232-B, Aug. 1969, (Reaffirmed Jun., 1981).
R. E. Fisher, "A Subscriber Set for the Equipment Test", The Bell System Technical Journal, Jan., 1979, pp. 123-143.
HMOS Single Chip Microcomputer Data Book, No. ADI 1207R1, 1987, pp. 5-1 through 5-5.
Motorola Semiconductor Technical Data, "8-Bit HMOS Microcomputer", MC68HC811D4, No. BR296, 1986, pp. 1-10.

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