Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
2000-01-10
2001-06-05
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S117000, C327S254000, C327S258000
Reexamination Certificate
active
06242953
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the design of integrated circuits, and more particularly, to multiplexed synchronization circuits for switching between frequency synthesized signals.
BACKGROUND OF THE INVENTION
It is often necessary in integrated circuit (IC) design to generate frequency synthesized signals. For example, a copy of a master clock may be divided to provide timing and control signals for internal IC functions that operate at different frequencies. The master clock copy typically is divided by a conventional divide-by-n circuit having a plurality of flip-flops. The divide-by-n circuit provides internal IC functions with a clock having a frequency equal to 1
the frequency of the master clock.
A synchronization problem, however, may arise when switching between the master clock copy and a divided master clock copy. The propagation delay added to the divided master clock copy by, for example, the flip-flops in the divide-by-n circuit, may spoil the synchronization between the master clock copy and the divided master clock copy. Moreover, if a multiplexer is used to select between the master clock copy and the divided master clock copy, additional propagation delay could be added to these clocks which may exacerbate the synchronization problem.
The prior art addresses the synchronization problem by providing a second clock source that operates at twice the frequency of the master clock to derive synchronized clocks. For example, some prior art may generate a synchronized, divided clock by dividing the second clock source by two and four, respectively. Unfortunately, the need to select between a divided and a non-divided copy of a master clock while maintaining synchronization between such clocks is not addressed by such prior art. Moreover, for applications that push the limits of semiconductor technology, it may be impossible to provide a second clock source that operates at twice the frequency of the master clock. Other prior art uses a phase-locked loop (PLL) to synchronize frequency synthesized clocks. Using a PLL, however, may prove too costly for certain applications.
Accordingly, there is a need for multiplexed synchronization circuits for switching between frequency synthesized signals without losing synchronization between such signals.
SUMMARY OF THE INVENTION
The present invention is directed to multiplexed synchronization circuits for switching frequency synthesized signals.
A plurality of selection circuits are used to generate synchronized slave signals from a common source signal. A first selection circuit and a second selection circuit generate from the source signal a first slave signal and a second slave signal, respectively. A third selection circuit and a fourth selection circuit are configured as a divide-by-n circuit for generating a third slave signal that is a divided version of the second slave signal. A fifth selection circuit provides a matching delay to preserve the synchronization between the first slave signal and the other slave signals. A sixth selection circuit is used to select between the second slave signal and the third slave signal in response to a select signal. A glitch prevention circuit may be used to provide the select signal and to guard against false selection of slave signals by the sixth selection circuit.
The present invention is also directed to a method of synchronizing signals. The method includes a step of generating a first slave signal and a second slave signal from a common source signal. The first slave signal is synchronized with the second slave signal. A next step includes generating a third slave signal from the source signal that is a synchronized, divided copy of the second slave signal. Another step includes switching between the second slave signal and the third slave signal in response to a select signal.
The present invention is further directed to multiplexed synchronization circuits for emulating, for example, the output signals of a flip-flop circuit. Such circuits are used as building blocks for a quad phase circuit having synchronized output signals that are 0°, 90°, 180°, and 270° out of phase with a common source signal.
The multiplexed synchronization circuits and methods described above switch frequency synthesized signals without losing synchronization between such signals, and without resorting to, for example, a second signal source operating at twice the frequency of the source signal. By not using a second source signal (e.g., PLL), chip area consumption is reduced.
These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings.
REFERENCES:
patent: 5635857 (1997-06-01), Flora
patent: 5767720 (1998-06-01), Osera et al.
patent: 5940467 (1999-08-01), Fransson
WO 97/30518 (Fransson, Counting Circuit), Aug. 1997.
3Dfx Interactive, Inc.
Cunningham Terry D.
Fenwick & West LLP
Tra Quan
LandOfFree
Multiplexed synchronization circuits for switching frequency... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiplexed synchronization circuits for switching frequency..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiplexed synchronization circuits for switching frequency... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2476207