Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1999-03-29
2003-09-02
Kizou, Hassan (Department: 2662)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S533000, C370S535000
Reexamination Certificate
active
06614814
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiplexed signal demultiplexing device, a transmission error measuring device and a transmission error measuring method, for carrying out a bit error test in order to measure errors when a signal is transmitted by a semiconductor, a transmission line or the like.
2. Description of the Related Art
Recently, various signals processed by a circuit comprising an IC (Integrated Circuit) or the like have been transmitted at higher speed in proportion to an improvement of a processing capacity of a processing unit. According to high speed transmission, it is desired that errors, such as data loss existing in a part of a transmitted signal or the like, are prevented from being caused by transmitting the signal.
In the step of manufacturing a semiconductor device or a transmission device, an error rate measuring device is used in order to discriminate a device having the property which is within the predetermined range, by measuring the error rate of the device or the like when the predetermined signal is transmitted by the device.
Hereinafter, the bit error measuring device
200
will be explained with reference to
FIGS. 5
,
6
A and
6
B as an embodiment of an error rate measuring device according to an earlier development.
FIG. 5
is a block diagram showing a constitution of the bit error measuring device
200
as an embodiment of an error rate measuring device according to an earlier development. As showing in
FIG. 5
, the bit error measuring device
200
inputs a signal generated by a transmitting unit
4
into an object
2
to be measured, which is a transmission line, and detects a signal outputted from the object
2
to be measured, by a receiving unit
5
. Because the receiving unit
5
detects whether the signal inputted into the object
2
to be measured is transmitted through the object
2
and is outputted from the object
2
without causing a bit error or not, it is possible to measure the error rate of the object
2
to be measured.
When a clock signal
4
b
is inputted into the transmitting unit
4
, the clock signal
4
b
is divided by a dividing circuit
51
with a frequency-dividing ratio of 1
in order to generate a 1
clock signal
51
a
. The 1
clock signal
51
a
is inputted into an address counter
10
. The address counter
10
counts up by synchronizing with the 1
clock signal
51
a
in order to obtain the count value by using m bits (m: integer). The count value obtained by the address counter
10
is outputted to a memory circuit
20
as an address number
10
a.
The memory circuit
20
outputs an n-bits data
20
a
having n bits (n: integer), which is assigned from a plurality of data stored therein by the address numbers
10
a
, to a multiplexing circuit
40
. The multiplexing circuit
40
multiplexes the n-bits data
20
a
inputted thereinto by synchronizing with the clock signal
4
b
in order to generate a test signal
40
a
, and outputs the test signal
40
a
to the object
2
to be measured.
The clock signal
4
b
and the test signal
40
a
are inputted into the object
2
to be measured. The object
2
to be measured outputs the test signal
40
a
inputted thereinto as a signal
5
a
to be measured, and outputs a clock signal
5
b.
When the signal
5
a
to be measured and the clock signal
5
b
are inputted into the receiving unit
5
, the signal
5
a
to be measured is demultiplexed by a demultiplexing circuit
52
in order to generate a demultiplexed signal
52
a
which is a n-bits data. The clock signal
5
b
is divided by the demultiplexing circuit
52
with a frequency-dividing ratio of 1
in order to generate a 1
clock signal
52
b
. The demultiplexed signal
52
a
and the 1
clock signal
52
b
are outputted to a data rearranging circuit
61
. Further, the 1
clock signal
52
b
is outputted to an address counter
11
.
The address counter
11
counts up by synchronizing with the 1
clock signal
52
b
in order to obtain the count value by using m bits (m: integer). The count value obtained by the address counter
11
is outputted to a memory circuit
21
as an address number
11
a
. The memory circuit
21
stores the same data as the memory circuit
20
therein. When the address number
11
a
is inputted into the memory circuit
21
from the address counter
11
, the memory circuit
21
outputs data stored in an address assigned by the address number
11
a
to a comparing circuit
70
as an n-bits data
21
a.
The demultiplexed signal
52
a
inputted into the data rearranging circuit
61
is outputted to the comparing circuit
70
as an n-bits data
61
a
. The comparing circuit
70
compares the n-bits data
21
a
outputted from the memory circuit
21
with the n-bits data
61
a
. The comparing circuit
70
detects that a bit of one n-bits data is not coincident with that of the other, which corresponds to the bit of one n-bits data, in order to output the results of the detection to a correspondence judging circuit
80
as a comparing signal
70
a
. When it is judged that many bits of the n-bits data
61
a
are not coincident with those of the n-bits data
21
a
on the basis of the result of comparing the two n-bits data by the comparing circuit
70
, the correspondence judging circuit
80
judges that the n-bits data
61
a
does not correspond to the n-bits data
21
a
, and outputs a correspondence judging signal
80
a
to a timing controlling circuit
90
.
Generally, when the comparing signal
70
a
is outputted from the comparing circuit
70
, it is thought that a data loss of a signal or an error thereof is caused by transmitting the signal through the object
2
to be measured. However, when the comparing signal
70
a
is too frequently outputted from the comparing circuit
70
, it is thought that the demultiplexing circuit
52
is wrongly operated.
That is, because many bits of the n-bits data
61
a
are not coincident with those of the n-bits data
21
a
when the signal obtained by demultiplexing the signal
5
a
to be measured with the demultiplexing circuit
52
is arranged in wrong order, the comparing signal
70
a
is frequently outputted from the comparing circuit
70
. The wrong operations of the demultiplexing circuit
52
are caused by non-coincidence of timing between the demultiplexed signal
52
a
and the test signal
40
a
or by non-correspondence of the data array between the n-bits data
61
a and the n-bits data
21
a
, which happens for some reasons when the demultiplexed signal
52
a
is generated by the multiplexing circuit
52
. In such a state, the bit error of the object
2
to be measured cannot be measured.
In this case, the so-called pull-in operations which will be explained in detail are carried out so that the n-bits data
61
a
can correspond to the n-bits data
21
a.
When the correspondence judging signal
80
a
outputted from the correspondence judging circuit
80
is inputted into the timing controlling circuit
90
, a data rearrangement controlling signal
61
b
is outputted from the timing controlling circuit
90
to a data rearranging circuit
61
in order to rearrange the demultiplexed signal
52
a
by the data rearranging circuit
61
. The data rearrangement controlling signal
61
b
inputted into the data rearranging circuit
61
has one value selected from n values having a range of 0 to (n−1).
For example, when the data having 32 bits from D
0
to D
31
is demultiplexed 4 bits each, there are four ways of arranging 4 bits including the bit D
4
. The first way is to assign the bit D
4
to the bottom of 4 bits. The second way is to assign the bit D
4
to the second bit from the bottom thereof. The third way is to assign the bit D
4
to the third bit from the bottom thereof. The fourth way is to assign the bit D
4
to the top thereof. In order to choose one way from the four ways, the data rearrangement controlling signal
61
b
has 4 values corresponding to the above four ways of arranging 4 bits. Therefore, because n-bits data is processed by the bit error measuring device
200
, the data
Ando Electric Co. Ltd.
Kizou Hassan
Oliff & Berridg,e PLC
Tsegaye Saba
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