Multiplexed real-time pyramid signal processing system

Details Multiplexed real-time pyramid signal processing system Multiplexed real-time pyramid signal processing system

1985-08-23

1987-11-24

Boudreau, Leo H.

Image analysis

Histogram processing

For setting a threshold

382 41, 382 42, 382 43, 358133, 364723, 364724, 364725, 364728, G06K 954

Patent

active

047093943

ABSTRACT:
The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.

REFERENCES:
patent: 4447886 (1984-05-01), Meeker
patent: 4603350 (1986-07-01), Arbeiter et al.
patent: 4674125 (1987-06-01), Carlson et al.
patent: 4694413 (1987-09-01), Arbeiter
C. Rochiere et al., Multirate Digital Signal Processing, published by Prentice Hall, Inc., 1983, pp. 79-88.
U.S. patent application Ser. No. 596,817, filed Apr. 4, 1984 by Carlson et al.
U.S. patent application Ser. No. 632,467, filed Jul. 19, 1984 by Arbeiter.

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