Multiplex communications – Channel assignment techniques – Combining or distributing information via time channels...
Reexamination Certificate
2000-02-03
2004-03-02
Vu, Huy D. (Department: 2665)
Multiplex communications
Channel assignment techniques
Combining or distributing information via time channels...
C370S458000, C370S463000
Reexamination Certificate
active
06700898
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to Ethernet devices. More particularly, it relates to an efficient and cost effective manner of allowing external access to internal Ethernet flags.
2. Background of Related Art
Ethernet is a widely-installed local area network (LAN) technology. Using an Ethernet interface, many computer devices can communicate with one another over a LAN. Ethernet is specified in a well known standard, IEEE 802.3.
An Ethernet LAN typically uses twisted pair wires or coaxial cable. The most commonly installed Ethernet systems are called 10Base-T and provide transmission speeds up to 10 megabits per second (Mbps).
Fast Ethernet, or 100Base-T, provides transmission speeds up to 100 Mbps. Fast Ethernet is typically used for LAN backbone systems, supporting workstations with 10Base-T interfaces. Gigabit Ethernet provides an even higher level of backbone support at 1000 Mbps.
Ethernet devices are connected to the Ethernet LAN and compete for access using a Carrier Sense Multiple Access with Collision Detection (CSMA/CD) type protocol.
Computer devices connected to the Ethernet LAN include an Ethernet interface (port). Initially, computer devices included a single Ethernet LAN interface (port). However, as computer networking became increasingly important in today's world, and as Ethernet has gained in popularity, computer needs now typically require more than one Ethernet port.
FIG. 6
shows a conventional Ethernet device (e.g., Ethernet integrated circuit)
600
including a plurality of Ethernet ports
602
,
604
,
606
. Each of the Ethernet ports
602
,
604
,
606
includes a data/address and LAN connection bus
610
,
612
,
614
and a status line bus of the physical layer transceiver for the Ethernet protocol (PHY)
616
,
618
,
620
, respectively. Typically, each status line bus
616
,
618
,
620
includes up to nine (9) separate status signals.
FIG. 7
shows in more detail conventional signals contained separately on a conventional Ethernet port status bus.
In particular, as shown in
FIG. 7
, the PHY status bus
700
includes an ACT signal
701
, a LINK signal
702
, a SPEED signal
703
, an FDUP signal
704
, a CS signal
705
, a TPJS signal
706
, a TPAPS signal
707
, an RS signal
708
, and an XS signal
709
.
The ACT signal
701
indicates activity on the respective Ethernet port. The LINK signal
702
indicates whether the relevant Ethernet port is up or down. The SPEED signal
703
indicates the speed of the Ethernet link, e.g., 10 Mb or 100 Mb. The FDUP signal
704
indicates whether the Ethernet link is full duplex or half duplex. The CS signal
705
is a carrier sense signal for the relevant Ethernet link. The TPJS signal
706
is a twisted pair jabber sense meaning that the receiver is detecting a jabber condition. The TPAPS signal
707
is a twisted pair auto polarity sense signal. The RS signal
708
is a receiving sense indicating whether or not the relevant Ethernet port is receiving. The XS signal
709
indicates whether or not the Ethernet port is transmitting.
In a typical Ethernet Transceiver device
600
, normally called PHY, each of the status signals (also called internal flags)
701
-
709
are output from the Ethernet device
600
to allow observation of the health of the Ethernet transceiver device
600
. For instance, each of the status signals
701
-
709
may be used to drive individual LEDs for visual inspection of the health of the Ethernet transceiver device
600
. Alternatively, or additionally, each of the separate status signals
701
-
709
may be input into an external register for read back by a processor or other device.
However, due to typical design limitations in the desired maximum number of external pins of a particular Ethernet transceiver device (particularly Ethernet transceiver devices having more than one Ethernet port), there is typically pressure on a designer to eliminate use of a number of the status signals, degrading the full observation capability of the Ethernet transceiver device
600
.
Alternatively, instead of eliminating some status signals, two different techniques are conventionally used to bring the internal status signals
701
-
709
external to a multi-port Ethernet transceiver device: A parallel technique and a serial technique. Oftentimes, the techniques may both be implemented in a particular multi-port Ethernet transceiver device, allowing operation in either a corresponding parallel mode or a corresponding serial mode.
In parallel mode, a subset of the status signals
701
-
709
are passed through directly onto a corresponding number of external pins. If all of the status signals
701
-
709
are to be made available for each Ethernet port, nine separate external pins for each Ethernet port will be required. Of course, fewer than all of the status signals
701
-
709
may be made available, but this would provide only a subset of all status signals, and thus a complete observation of the operation of each of the Ethernet ports is not possible.
In serial mode, the status signals
701
-
709
are serialized and passed external to the Ethernet transceiver device
600
using a data pin, a clock pin, and any control pins if desired. Serial transmission of the status signals
701
-
709
minimizes the external pin count in multi-port Ethernet transceiver devices
600
, but increases the cost and complexity of the external board because the serialized status signals
701
-
709
must be converted from serial back into separate, parallel signals. Thus, using serial transmission techniques to pass the status signals
701
-
709
external to the Ethernet transceiver device, complex external logic is required to capture and analyze the serial stream data containing the internal status signals.
There is a need for a technique and device which both minimizes external pin count requirements while at the same time provides all available status signals for each Ethernet port external to the Ethernet transceiver device.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a multi-port Ethernet device comprises a plurality of Ethernet ports, and an internal multiplexer. The plurality of Ethernet ports correspond to a respective plurality of status signal busses. The plurality of status signal busses are input to the internal multiplexer. A common status bus output from the multiplexer is available at external pins of the Ethernet device. A port valid signal indicates which of the plurality of status signal busses is being output by the internal multiplexer.
A method of minimizing external pins in a multi-port Ethernet device in accordance with another aspect of the present invention comprises multiplexing status signals from each of a plurality of Ethernet ports in the Ethernet device into a common status signal bus. The multiplexed status signals are output over a common set of external pins of the. Ethernet device.
A method of minimizing external pins in a multi-port Ethernet device in accordance with yet another aspect of the present invention comprises sequentially outputting a parallel representation of a status of each of a plurality of Ethernet ports over a common set of external pins of the Ethernet device.
REFERENCES:
patent: 4037199 (1977-07-01), Rozehnal et al.
patent: 4630193 (1986-12-01), Kris
patent: 5276443 (1994-01-01), Gates et al.
patent: 5555436 (1996-09-01), Gavish
patent: 5598418 (1997-01-01), Lo et al.
patent: 5819112 (1998-10-01), Kusters
patent: 5874930 (1999-02-01), McRobert et al.
patent: 6058427 (2000-05-01), Viswanath et al.
patent: 6483849 (2002-11-01), Bray et al.
Barakat Edmond H.
Manzella Joseph A.
Agere Systems Inc.
Bollman William H.
Ryman Daniel
Vu Huy D.
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