Multiplexed output circuit and method of operation thereof

Details Multiplexed output circuit and method of operation thereof Multiplexed output circuit and method of operation thereof

1997-03-21

1999-02-02

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

327408, 327409, H01P 900, H03F 156

Patent

active

058670530

ABSTRACT:
A multiplexed output circuit (200) for use in an integrated circuit (500) such as a static random access memory locates a plurality of amplifiers (206, 208), a plurality of output buffers (210, 212), and an output driver (201) on the integrated circuit (500), such that the routing parasitic delay between the plurality of output buffers and the output driver (218-224) is greater than the routing parasitic delay between any output buffer (e.g. 212) and its corresponding amplifier (e.g. 206).

REFERENCES:
patent: 4855614 (1989-08-01), Maitre
patent: 4959873 (1990-09-01), Flynn et al.
patent: 4972157 (1990-11-01), Moyal
patent: 5463326 (1995-10-01), Raje

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