Static information storage and retrieval – Powering
Reexamination Certificate
2000-01-13
2001-04-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Powering
C365S149000, C365S189090, C365S205000, C365S206000, C365S191000
Reexamination Certificate
active
06219294
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor memory devices and, more particularly to a multiplexed noisy-quiet power busing scheme for improved area efficiency and pause performance in dynamic random access memories.
2. Description of the Related Art
An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1
illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells
10
. Each cell
10
contains a storage capacitor
14
and an access field effect transistor or transfer device
12
. For each cell, one side of the storage capacitor
14
is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of the storage capacitor
14
is connected to the drain of the transfer device
12
. The gate of the transfer device
12
is connected to a signal known in the art as a word line
18
. The source of the transfer device
12
is connected to a signal known in the art as a bit line
16
(also known in the art as a digit line). With the memory cell
10
components connected in this manner, it is apparent that the word line
18
controls access to the storage capacitor
14
by allowing or preventing the signal (representing a logic “0” or a logic “1”) carried on the bit line
16
to be written to or read from the storage capacitor
14
. Thus, each cell
10
contains one bit of data (i.e., a logic “0” or logic “1”).
Referring to
FIG. 2
, an exemplary DRAM circuit
40
is illustrated. The DRAM
40
contains a memory array
42
, row and column decoders
44
,
48
and a sense amplifier circuit
46
. The memory array
42
consists of a plurality of memory cells (constructed as illustrated in
FIG. 1
) whose word lines and bit lines are commonly arranged into rows and columns, respectively. The bit lines of the memory array
42
are connected to the sense amplifier circuit
46
, while its word lines are connected to the row decoder
44
. Address and control signals are input into the DRAM
40
and connected to the column decoder
48
, sense amplifier circuit
46
and row decoder
44
and are used to gain read and write access, among other things, to the memory array
42
.
The column decoder
48
is connected to the sense amplifier circuit
46
via control and column select signals. The sense amplifier circuit
46
receives input data destined for the memory array
42
and outputs data read from the memory array
42
over input/output (I/O) data lines. Data is read from the cells of the memory array
42
by activating a word line (via the row decoder
44
), which couples all of the memory cells corresponding to that word line to respective bit lines, which define the columns of the array. One or more bit lines are also activated. When a particular word line is activated, the sense amplifier circuit
46
connected to a bit line column detects and amplifies the data bit transferred from the storage capacitor of the memory cell to its bit line by measuring the potential difference between the activated bit line and a reference line which may be an inactive bit line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
Typically, the memory of a DRAM is subdivided into quadrants of memory. A quadrant may contain a bank, partial bank, multiple banks or multiple partial banks. In addition, a bank will contain one or more sub arrays.
FIG. 3
illustrates the DRAM
40
with a memory array
42
&Dgr; that is subdivided into four quadrants Q
1
, Q
2
, Q
3
, Q
4
.
FIG. 4
illustrates how the DRAM memory quadrants are also often further subdivided into sub arrays S
1
, S
2
, . . . S
N
. Each sub array S
1
, S
2
, . . . S
N
is connected to respective local row decoders
44
1
,
44
2
, . . .
44
N
and sense amplifier circuits
46
1
,
46
2
, . . .
46
N
(other circuitry such as a column decoder and the I/O lines are not shown). In addition, a gap
58
1
,
58
2
, . . .
58
N
is found at respective intersections of the local row decoders
44
1
,
44
2
, . . .
44
N
and sense amplifier circuits
46
1
,
46
2
, . . .
46
N
for each sub array S
1
, S
2
, . . . S
N
. Although not required, these gaps
58
1
,
58
2
, . . .
58
N
typically include sense amplifier control circuitry (illustrated in
FIG. 5
) used to control associated sense amplifier circuits
46
1
,
46
2
, . . .
46
N
. The sense amplifier control circuitry is usually contained within the gaps
58
1
,
58
2
, . . .
58
N
to conserve precious space on the DRAM chip.
Referring now to
FIGS. 4 and 5
, a control circuit
60
is connected to the sense amplifier control circuitry
64
of each gap
58
1
,
58
2
, . . .
58
N
(designated in
FIG. 5
as gap
58
X
) via sense amplifier control lines LPSA_, LNSA. The sense amplifier control circuit
64
(
FIG. 5
) contains a p-channel metal-oxide semiconductor field-effect transistor (MOSFET)
66
and an n-channel MOSFET
68
. A voltage bus, designated generally as V
CC
or V
CC
bus, is connected to a source terminal of the p-channel MOSFET
66
. A ground potential bus, designated generally as GND or GND bus, is connected to a source terminal of the n-channel MOSFET
68
. It should be noted that the sense amplifier control circuitry
64
would also contain additional circuitry, such as conventional biasing circuitry, but the additional circuitry is not pertinent to the present invention.
The first sense amplifier control signal LPSA_ is used to activate the p-channel MOSFET
66
during a row activation process. When activated, the MOSFET
66
switches in the voltage from the V
CC
bus to generate a p-sense amplifier activation signal ACT. As is known in the art, the p-sense amplifier activation signal ACT is used to activate a p-sense amplifier portion (not shown) of the sense amplifier circuit
46
X
during a row activation operation. The second sense amplifier control signal LNSA is used to activate the n-channel MOSFET
68
during a row activation operation. When activated, the MOSFET
68
switches in the ground potential from the GND bus to generate an n-sense amplifier activation signal RNL_. As is known in the art, the n-sense amplifier activation signal RNL_ is used to activate an n-sense amplifier portion (not shown) of the sense amplifier circuit
46
X
during a row activation operation. It should be appreciated that the particular circuitry of the sense amplifier circuit
46
X
is not pertinent to the practice of the invention.
Referring to
FIG. 6
, it can be seen that prior to the generation of the p-sense amplifier activation signal ACT and the n-sense amplifier activation signal RNL_, that the VCC bus is at a potential equivalent to Vcc, while the GND bus is at a GND potential. Immediately after the generation of the ACT and RNL_ signals, the potential of the V
CC
bus drops below Vcc, while the potential of the GND bus rises above the GND potential. That is, immediately after the generation of the ACT and RNL_ signals, the V
CC
bus experiences a “bump” down in voltage, while the GND bus experiences a “bump” up in voltage (hereinafter, these bumps will be collectively referred to as “power bumps”). These power bumps occur because there is a large current drain when the sense amplifier circuitry becomes active.
Eventually, the power pumps decay back to the Vcc and GND potentials. As shown in
FIG. 6
, however, a series of ACT and RNL_ signals
Fardad Mansour
Huber Brian W.
Norwood Roger D.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Ho Hoai V.
Micro)n Technology, Inc.
Nelms David
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