Multiplexed encoder and decoder with address mark generation/che

Details Multiplexed encoder and decoder with address mark generation/che Multiplexed encoder and decoder with address mark generation/che

1989-10-30

1991-07-02

Shoop, Jr., William M.

Coded data generation or conversion

Digital code to digital code converters

To or from run length limited codes

360 48, 341 56, H03M 700, G11B 509

Patent

active

050289225

ABSTRACT:
A two-level multiplexed encoder/decoder based on a novel technique of code table compression is disclosed. By means of comparing various code conversion tables such as well-known tables for use in NRZ-MRM, NRZ-RLL conversion schemes, separate code word condition sets are obtained. In accordance with the code word condition sets thus obtained, a two-level multiplexed encode and decode logic can be easily constructed. The code word condition sets representing the compressed code relations are sensed in the first level and are used further to set up the operation of a connected network of a multiplexed logic circuit in the second level. The AM generation/check and precompensation circuit necessary for the encoder and decoder are incorporated as an integral part. This method is applicable when more than two code tables are needed to be integrated in a single encoder/decoder.

REFERENCES:
patent: 4118791 (1978-10-01), Swain
patent: 4373152 (1983-02-01), Jacobsthal
patent: 4420771 (1983-12-01), Pirsch
patent: 4551773 (1985-11-01), Cohn et al.
patent: 4651237 (1987-03-01), Williams
patent: 4691254 (1987-09-01), Cloke
patent: 4728929 (1988-03-01), Tanaka
patent: 4841299 (1989-06-01), Wraver
patent: 4884074 (1989-11-01), Nourry et al.

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