Multiplexed bus architecture for configuration sensing

Details Multiplexed bus architecture for configuration sensing Multiplexed bus architecture for configuration sensing

1988-07-18

1989-09-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307242, 307473, 307468, 364716, 34082591, G06F 1120, G05B 2402, H03K 19094, H03K 1704

Patent

active

048663093

ABSTRACT:
The invention provides a circuit for use with a standard bidirectional databus having an active current device providing a first logic level in combination with a selectably jumpered passive resistance device providing a second logic level, the active element responsive to an enable signal whereby tristating the bus write drivers and reading the bus will sense a configuration determined by selection of the jumper.

REFERENCES:
patent: 4486753 (1984-12-01), Saeki et al.
patent: 4608504 (1986-08-01), Yamamoto
patent: 4673830 (1987-06-01), Giorgetta et al.
patent: 4697095 (1987-09-01), Fujii
patent: 4736115 (1988-04-01), Storey
patent: 4746815 (1988-05-01), Bhatia et al.
patent: 4808844 (1989-02-01), Ozaki et al.

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