Boots – shoes – and leggings
Patent
1983-08-08
1987-06-23
Williams, Archie E.
Boots, shoes, and leggings
365230, G06F 1200, G11C 800
Patent
active
046758089
ABSTRACT:
Disclosed is a computer system (FIG. 1) that is operable with any multiplexed-address memory (200) within a size range of 2.sup.N to 2.sup.N+R memory locations (211). The system has a memory of 2.sup.S locations selected from the predetermined range, and the memory has S/2 multiplexed address input terminals (231). Address bits forming a memory address, generated for example by a processor (400), are multiplexed by a memory controller (300) onto N/2+R address output terminals (314) in two sets of N/2+R address bits. The address bit sets have at least R/2 bits in common. An address bus (250) transports the multiplexed address bits to the memory. The bus has N/2+R address leads (251) connected to the output terminals of the memory controller. S/2 of those address leads are also connected to the address input terminal of the memory. The remaining address leads are not connected. The memory controller multiplexes the address of any memory within the predetermined range onto its output terminals. Addressing of a different-size memory requires merely connecting the memory to the appropriate address leads of the multiplexed-address bus.
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Grinn James M.
McWethy Kevin A.
American Telephone and Telegraph Company AT&T Bell Laboratories
Lee Thomas L.
Volejnicek David
Williams Archie E.
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