Multiplex digital echo suppression system

Details Multiplex digital echo suppression system Multiplex digital echo suppression system

1976-02-25

1977-09-27

Claffy, Kathleen H.

1791706, H04B 320

Patent

active

040513327

ABSTRACT:
The invention discloses a multiplex digital echo suppression system in which on each of the transmitting and receiving sides the PCM signal for each channel is converted into the parallel signal and also into the absolute value signal representing the absolute value of the PCM signal by eliminating the sign bit; thus converted signals are accumulated for a predetermined time in a transmitting-side and receiving side accumulators and then compared in a comparator so that the output is derived from the comparator when the accumulated signal in the transmitting-side accumulator is higher in level than the signal accumulated in the receiving-side accumulator; in response to the output signal from the comparator, a first timer is set to a first predetermined time during which the signal is derived from the first timer; when the signal level in the receiving-side accumulator is higher than a predetermined level of a threshold level comparator, the output is derived therefrom and applied to a second timer which in turn is set to a second predetermined time shorter than the time of the first timer, the output signal being derived from the second timer during said second predetermined time. The output from the first timer is applied to a receiving-side logic circuit which in turn controls an attenuator while the outputs from the first and second timers are applied to a transmitting-side logic circuit which controls an echo switch by the logical combination of said output signals.

REFERENCES:
patent: 3562448 (1971-02-01), May, Jr.
patent: 3673355 (1972-06-01), La Marche et al.
patent: 3823275 (1974-07-01), La Marche et al.
patent: 3937907 (1976-02-01), Campanella et al.

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