Multiplex bus system with duty cycle correction

Details Multiplex bus system with duty cycle correction Multiplex bus system with duty cycle correction

2003-02-07

2009-12-22

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C327S172000

Reexamination Certificate

active

07636410

ABSTRACT:
The present invention is related to a method for treating a digital signal within a protocol handler which is part of a module coupled to a multiplex bus. The method consists in detecting the duty cycle of the digital signal, and in modifying said digital signal so that the modified signal contains the same data, but has a duty cycle of approximately 50%.

REFERENCES:
patent: 5367200 (1994-11-01), Leonida
patent: 5412698 (1995-05-01), Van Brunt et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 5757218 (1998-05-01), Blum
patent: 6917656 (2005-07-01), Fuhrmann et al.
patent: 2002/0017950 (2002-02-01), Shimoda
patent: 2002/0044618 (2002-04-01), Buchwald et al.
patent: 2002/0196883 (2002-12-01), Best et al.
patent: 2004/0091273 (2004-05-01), Brissette et al.

Affiliated with

Also associated with

Rating

Multiplex bus system with duty cycle correction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiplex bus system with duty cycle correction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiplex bus system with duty cycle correction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4132531