Multiplex address/data bus with multiplex system controller and

Details Multiplex address/data bus with multiplex system controller and Multiplex address/data bus with multiplex system controller and

1993-06-11

1998-08-11

Sheikh, Ayaz R.

G06F 300

Patent

active

057939900

ABSTRACT:
A computer system having a multiplex address/data bus with a multiplex system controller and method therefor is disclosed which provides in a computer system having time shared use of a multiplex address/data bus to reduce the number of required pins for devices within the computer system, a CPU having at least one address bus, at least one data bus, at least one memory input/output, and at least one CPU control bus coupled thereto for sending and receiving information. In addition, this system includes at least one memory input/output device coupled to a first portion of the address bus for sending and receiving at least one of address information and data information, at least one input/output only device coupled to a second portion of the address bus for sending and receiving at least one of address information and data information, and a multiplex system controller coupled to the CPU and the address bus and having a multiplex control bus coupled to both the memory input/output device and to the input/output only device for taking control of the address bus from the CPU.

REFERENCES:
patent: 4112490 (1978-09-01), Pohlman et al.
patent: 4286321 (1981-08-01), Baker et al.
patent: 4403283 (1983-09-01), Myntti et al.
patent: 4675808 (1987-06-01), Grinn et al.
patent: 4860198 (1989-08-01), Takenaka
patent: 4987529 (1991-01-01), Cratt et al.
patent: 5214767 (1993-05-01), Wanner et al.

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