Multiple writes per a single erase for a nonvolatile memory

Details Multiple writes per a single erase for a nonvolatile memory Multiple writes per a single erase for a nonvolatile memory

1996-07-22

1999-08-10

Nelms, David

Static information storage and retrieval

Floating gate

Multiple values

365168, 36518529, 3651853, G11C 1134

Patent

active

059368845

ABSTRACT:
A method of performing multiple writes before erasing a memory cell is described. M bits are stored in a first group of levels of the memory cell. M subsequent superseding bits are stored in a second group of levels of the memory cell without erasing the memory cell. Another method of writing to a memory cell includes the step of storing m bits in a first group of levels of the memory cell. A group indicator is adjusted to identify a subsequent group of levels of the memory cell. Next, m superseding subsequent bits are stored in the subsequent group of levels, without erasing the memory cell. The steps of adjusting the group indicator and storing m superseding subsequent bits are repeated. A method of deferring an erase for a memory cell is also described. A group indicator is adjusted to identify a group of 2.sup.m adjacent levels of the memory cell available for storing an m bit value. A method of reading a memory cell includes providing a group indicator. The group indicator identifies a group of 2.sup.m adjacent levels of the memory cell. An m bit value is then read by sensing the group of 2.sup.m adjacent levels identified by the group indicator.

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