Multiple word width memory array clocking scheme for reading wor

Details Multiple word width memory array clocking scheme for reading wor Multiple word width memory array clocking scheme for reading wor

1996-01-11

1997-10-28

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Counting

365233, 365239, 365221, G11C 700, H01L 2710

Patent

active

056823568

ABSTRACT:
The present invention provides a circuit for distributing data from a number of individual memory cells in a memory array to a common output. The present invention uses a multi-bit counter to distribute a timing signal to a number of sense amplifier blocks. Each of the sense amplifier blocks receives both a data input signal from the memory array and the timing signal at all times. When a particular timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from the corresponding memory array and is presented to the output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to read multiple width words from the memory array.

REFERENCES:
patent: 4802122 (1989-01-01), Auvinen et al.
patent: 4839866 (1989-06-01), Ward et al.
patent: 4875196 (1989-10-01), Spaderna et al.
patent: 4891788 (1990-01-01), Kreifels
patent: 5084837 (1992-01-01), Matsumoto et al.
patent: 5088061 (1992-02-01), Golnabi et al.
patent: 5228002 (1993-07-01), Huang
patent: 5262996 (1993-11-01), Shiue
patent: 5305253 (1994-04-01), Ward
patent: 5311475 (1994-05-01), Huang
patent: 5317756 (1994-05-01), Komatsu et al.
patent: 5367486 (1994-11-01), Mori et al.
patent: 5404332 (1995-04-01), Sato et al.
patent: 5406273 (1995-04-01), Nishida et al.
patent: 5406554 (1995-04-01), Parry
patent: 5462612 (1995-10-01), Ichige et al.
patent: 5467319 (1995-11-01), Nusinov et al.
patent: 5490257 (1996-02-01), Hoberman et al.
patent: 5506809 (1996-04-01), Csoppenszky et al.
patent: 5513318 (1996-04-01), van de Goor et al.
patent: 5521876 (1996-05-01), Hattori et al.
patent: 5546347 (1996-08-01), Ko et al.
Roland T. Knaack, U.S.S.N. 08/559,983, Multiple Word Width Memory Arry Clocking Scheme, filed Nov. 17, 1995.

Affiliated with

Also associated with

Rating

Multiple word width memory array clocking scheme for reading wor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple word width memory array clocking scheme for reading wor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple word width memory array clocking scheme for reading wor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1030313