Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2004-07-26
2011-12-13
Bullock, Jr., Lewis (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S490000
Reexamination Certificate
active
08078661
ABSTRACT:
A multiple-word multiplication-accumulation circuit suitable for use with a single-port memory. The circuit is composed of a multiplication-accumulation (MAC) operator and surrounding registers. The MAC operator has multiplicand and multiplier input ports with different bit widths to calculate a sum of products of multiple-word data read out of a memory. The registers serve as buffer storage of multiple-word data to be supplied to individual input ports of the MAC operator. The amount of data supplied to the MAC operator in each clock cycle is adjusted such that total amount of data consumed and produced by the MAC operator in one clock cycle will be equal to or smaller than the maximum amount of data that the memory can transfer in one clock cycle. This feature enables the use of a bandwidth-limited single-port memory, without causing adverse effect on the efficiency of MAC operator usage.
REFERENCES:
patent: 5522085 (1996-05-01), Harrison et al.
patent: 5583804 (1996-12-01), Seal et al.
patent: 5787025 (1998-07-01), Muwafi et al.
patent: 5847981 (1998-12-01), Kelley et al.
patent: 5941940 (1999-08-01), Prasad et al.
patent: 6484194 (2002-11-01), Henderson et al.
patent: 6557022 (2003-04-01), Sih et al.
patent: 6564238 (2003-05-01), Kim et al.
patent: 6957242 (2005-10-01), Snyder
patent: 1 217 512 (2001-11-01), None
patent: 2002-207589 (2002-07-01), None
Montgomery, “Modular Multiplication Without Trial Division”, Mathematics of Computation, vol. 44, No. 170, pp. 519-520 (1985).
Koç, “High-Speed RSA Implementation”, Technical Report TR 201, RSA Laboratories, Version 2.0, pp. 48-59 (1994).
Cetin Kaya Koc, et al.; “Analyzing and Comparing Montgomery Multiplication Algorithms”; IEEE Micro.; Jun. 1996; vol. 16, No. 3, pp. 26-33.
Cetin Kaya Koc; “High-Speed RSA Implementation”; RSA Laboratories; 1994; pp. 1-70.
Alexandre F. Tenca, et al.; “A Scalable Architecture for Montgomery Multiplication”; Cryptographic Hardware and Embedded Systems Int'l Workshop; Aug. 12, 1999; pp. 94-108.
Masui Shoichi
Mukaida Kenji
Takenaka Masahiko
Torii Naoya
Bullock, Jr. Lewis
Fujitsu Patent Center
Fujitsu Semiconductor Limited
Yaary Michael
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