Multiple width data bus for a microsequencer bus controller syst

Details Multiple width data bus for a microsequencer bus controller syst Multiple width data bus for a microsequencer bus controller syst

1993-12-23

1996-05-07

Beausoliel, Jr., Robert W.

Excavating

371 492, G06F 1134

Patent

active

055155073

ABSTRACT:
A bus architecture and associated circuitry for providing communication between processors and multiple gate arrays whereby the size of the data being transferred may be either full words of 32-bits or 36-bits per word, or half words of 16-bits or 18-bits per word. Parity generation logic operates on the data to be sent over the bus to generate a parity value from the correct data bits depending on the selected data word size. Parity checking logic operates on the data received from the bus to check the parity of the correct data bits depending on the selected data word size.

REFERENCES:
patent: 4453215 (1984-06-01), Reid
patent: 4486826 (1984-12-01), Wolff et al.
patent: 4597084 (1986-06-01), Dynnson et al.
patent: 4654857 (1987-03-01), Sammon et al.
patent: 4663729 (1987-05-01), Matick
patent: 4667305 (1987-05-01), Dill
patent: 4750177 (1988-06-01), Hendrie et al.
patent: 5113369 (1992-05-01), Kinoshita
patent: 5255376 (1993-10-01), Frank

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