Multiple voltage supplies for field programmable gate arrays and

Details Multiple voltage supplies for field programmable gate arrays and Multiple voltage supplies for field programmable gate arrays and

1991-11-25

1993-08-24

LaRoche, Eugene R.

Static information storage and retrieval

Powering

365154, G11C 1100

Patent

active

052395103

ABSTRACT:
A field programmable array of application circuitry (C1, C2, . . .) is programmed (or reprogrammed) by first applying application circuitry power supply (AV.sub.dd =5v) to the application circuitry, and then applying a binary digital data signal (D0/D1) through the source-drain path of an access transistor (N3) in its on condition to the SRAM that controls the on/off condition of its associated controlled pass transistor (N4). This SRAM is typically one of a row-column array of similar SRAMs, and the access transistors for all SRAMs on the same row are similarly supplied with data signals through access transistors. The source-drain path of each pass transistor is connected between a separate pair of application circuitry interconnection points (A1, A2), whereby the on/off condition of this pass transistor determines whether or not these two points are going to be connected after the programming (or reprogramming) is terminated. While the data signal (D0/D1) is thus being applied to the SRAM, and while the power supply (PV.sub.DD) for the SRAM is being maintained at an intermediate level (3v) below the level of the application circuitry power supply voltage (AV.sub.dd =5v) and below the high binary level (D1), a row-select pulse (S) is applied to a control terminal of the access transistor, as well as to all control terminals of access transistors for accessing all other SRAMs on the same row as the SRAM under discussion. The row-select pulse (S) is then terminated and the SRAMs on other rows (if need be) are similarly written (or rewritten). Then the power supply (PV.sub.DD) for the SRAMs is increased to a level (PV.sub.DD =6v) advantageously higher, by a threshold of the pass transistor (N4), than that of the application circuitry (AV.sub.dd =5v), to reduce both voltage drops and power losses in pass transistors. In CMOS technology, in each SRAM the p-channel MOS transistor in both (cross-coupled) inverters have the same thresholds.

REFERENCES:
patent: 4270188 (1981-05-01), Saito
patent: 4271487 (1981-06-01), Crayeraft et al.
patent: 4821233 (1989-04-01), Hsieh
patent: 5065362 (1991-11-01), Herdt et al.

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