Multiple voltage compatible I/O buffer

Details Multiple voltage compatible I/O buffer Multiple voltage compatible I/O buffer

2000-08-08

2001-11-27

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S077000, C327S333000, C327S081000

Reexamination Certificate

active

06323704

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to I/O buffer circuitry, and in particular, the resent invention relates to I/O buffer circuitry which is compatible with multiple voltage levels.
RELATED ART
A typical integrated circuit (IC) includes input/output (I/O) buffer circuitry for interfacing with external connections such as bus connections. Since various bus standards exist, each I/O buffer must be designed to be compatible with the bus standard with which the IC will be used. For example, there are multiple standards for Peripheral Component Interconnect (PCI) buses. In one PCI standard, the PCI bus operates at a voltage of 3.3 volts. In another PCI standard, the PCI bus operates at a voltage of 5 volts. As a result, if a connection pad of an IC is intended to be used with a 3.3 volt PCI bus, the buffer circuitry associated with that pad must be designed to handle a 3.3 volt bus. Similarly, if a connection pad of the IC is intended to be used with a 5 volt PCI bus, the buffer circuitry associated with that pad must be designed to handle a 5 volt bus without transistor break down. This circuitry is a solution for preventing a break down voltage applied on transistors of the buffer and to guarantee the voltage difference across the transistors to be no larger than a predetermined safe voltage (e.g. 4.1 volts). Therefore, prior art buffer circuitry is designed to work with a single desired standard. This requires a designer to design buffer circuitry based on the type of bus with which the buffer will be used.


REFERENCES:
patent: 5438280 (1995-08-01), Sugawara
patent: 5512844 (1996-04-01), Nakakura et al.
patent: 6150843 (2000-11-01), Shiffer et al.

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