Multiple virtual address translation per computer cycle

Details Multiple virtual address translation per computer cycle Multiple virtual address translation per computer cycle

1991-05-07

1994-08-23

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 364DIG2, G06F 1210

Patent

active

053414853

ABSTRACT:
Dynamic address translation structures and procedures are capable of multiple address translations for the same processor in a single cycle. According to one approach, a plurality of directory look aside tables (DLATs) are used to provide multiple address translation. The DLATs are accessed in parallel by separate virtual address generators. To avoid the problem of generating the same address multiple times for each of the DLATs, a generated address for one DLAT may be written to all the DLATs or, alternatively, if a miss occurs in one DLAT, a search is made of the other DLATs before the address is generated. In the former case, an address written to all the DLATs may overwrite an address that will be needed for a future translation by one of the other DLATs. This is avoided in the latter case, but translations in other DLATs are interrupted when a miss occurs in one of the DLATs. This, in turn, may be avoided by employing "shadow" DLATs which are copies of the DLATs. The shadow DLATs are searched when a miss occurs in one of the DLATs thereby avoiding any interruption of translations by the DLATs themselves. Rather than use multiple DLATs, a single interleaved DLAT may be used by multiple address generators.

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