Multiple time programmable (MTP) PMOS floating gate-based...

Details Multiple time programmable (MTP) PMOS floating gate-based... Multiple time programmable (MTP) PMOS floating gate-based...

2006-08-23

2009-06-02

Le, Vu A (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185030

Reexamination Certificate

active

07542342

ABSTRACT:
A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

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