Multiple tilted angle ion implantation MOSFET method

Details Multiple tilted angle ion implantation MOSFET method Multiple tilted angle ion implantation MOSFET method

1993-07-22

1994-12-13

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 44, 437907, 257344, H01L 21265

Patent

active

053729579

ABSTRACT:
A method is described for fabricating a lightly doped drain MOS FET integrated circuit device which is useful for sub-half micron ground rules integrated circuits. A pattern of gate electrode structures is formed upon a semiconductor substrate which structures each includes a gate oxide and a polysilicon layer. A pattern of lightly doped regions in the substrate are formed under the structures by multiple ion implantations. After the ion implantations the lightly doped regions are annealed at a temperature and time to cause a critical and desired dopant diffusion. A dielectric spacer structure is formed upon the sidewalls of each of the structures and over the adjacent portions of the substrate. A pattern of heavily doped regions is formed in the substrate adjacent to the dielectric spacer structure on the sidewalls of the structures and over the adjacent portions of the substrate which form lightly doped drain source/drain structures of an MOS FET device to form said integrated circuit device.

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"1/4.mu.m LATID (Large-Tilted-Angled Implanted Drain) Technology" by T. Hori, published in IEDM '89, pp. 777/780.
"Graded-Junction Gate/N-Overlapped LDD MOSFET Structures For High Hot-Carrier Reliability" by Y. Okumura et al, published in IEEE Transactions on Electron Devices, vol. 38, No. 12, Dec. 1991, pp. 2647-2656.

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