Multiple terminal SMT BGA-style wound capacitor

Details Multiple terminal SMT BGA-style wound capacitor Multiple terminal SMT BGA-style wound capacitor

2001-09-28

2003-03-04

Dinkins, Anthony (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S301500, C361S311000

Reexamination Certificate

active

06529365

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to capacitors. More particularly, the invention relates to a ball grid array (BGA) style capacitor having a reduced equivalent series resistance (ESR) and equivalent series inductance (ESL).
2. Discussion
In the highly-competitive personal computer (PC) industry, the difficult trade-off between cost and performance has been well documented. For example, in an effort to provide more features to the consumer at a lower cost, significant focus has been placed on streamlining motherboard systems and components. Most motherboards employ one or more voltage regulation circuits to ensure that the proper reference voltages are supplied to the motherboard processors and it has been determined that such a circuit has a direct effect on the switching performance of the processor. The voltage regulation circuit typically has a voltage regulation module and a capacitor arrangement (among other components). The capacitor arrangement is critical because it provides decoupling between the voltage regulation module (VRM) and the processor. Conventional approaches to the capacitor arrangement involve the use of multiple high performance bulk-type capacitors, which can have very low equivalent series resistance (ESR), temperature stability, wide frequency range and long life. Low ESR reduces the unwanted parasitic impedance and heating effects that degrade capacitors and is highly desirable in the computing industry. The cost of these performance capacitors, however, is relatively high with respect to other capacitors. It is therefore desirable to provide an alternative to conventional performance capacitors in voltage regulation circuits.
The alternative approach to the above design would be to use a combination of ceramic and conventional electrolytic capacitors, which would reduce the costs of the capacitor arrangement considerably. The trade-off to reduced cost, however, is reduced performance under conventional approaches.
Thus, the conventional capacitor arrangement provides a significant cost saving opportunity, but certain difficulties remain. For example, the typical wound aluminum electrolytic capacitor is unable to meet the exacting ESR and equivalent series inductance (ESL) requirements of modem day high speed processors.
FIGS. 1-3
illustrate that the conventional wound capacitor
10
has a case
12
, a winding
14
disposed within the case
12
and a dual lead configuration
16
. The dual lead configuration
16
is coupled to the winding
14
and extends from the case
12
for connection to an external printed wiring board (PWB, not shown). It can be seen that the dual lead configuration
16
has a cathode terminal assembly
18
and anode terminal assembly
20
. Each terminal assembly
18
,
20
includes a termination
22
(
22
a
,
22
b
), a lead
24
(
24
a
,
24
b
), and a weld
26
(
26
a
,
26
b
) coupling the termination
22
to the lead
24
.
It has been determined that the design of the dual lead configuration
16
can be quite challenging with regard to ESR and ESL. For example, limiting the lead configuration to two terminal assemblies has been found to contribute to a relatively high ESR in a capacitor of this type. The distance between terminal assemblies
18
and
20
has a significant impact on ESR and ESL.
It is also important to note that the weld
26
contributes to loop ESL and that the relatively long two-piece termination/lead design adds to both loop ESL and ESR. It is therefore desirable to provide a lead configuration that enables ESR to be reduced without sacrificing with respect to ESL.
It will also be appreciated that certain manufacturing and placement difficulties can also result from the conventional capacitor
10
. For example, the typical solder connection that occurs at the leads
24
requires wave soldering, which prohibits the use of the capacitor
10
in dual-sided reflow PWBs. Furthermore, the traditional case
12
can be relatively tall, which limits the use of the capacitor
10
to applications having a great deal of clearance space. Tall body and long leads contribute to higher ESR/ESL as well. Redesign of the height could bring the ESR/ESL down. It is therefore desirable to provide a solution that enables dual-sided reflow techniques commonly used in surface mount technologies (SMT), and greater flexibility in capacitor placement.


REFERENCES:
patent: 3988650 (1976-10-01), Fritze
patent: 4916576 (1990-04-01), Herbert et al.
patent: 5359487 (1994-10-01), Carrico et al.
patent: 6110233 (2000-08-01), O'Phelan et al.
patent: 6194979 (2001-02-01), Bloom et al.
patent: 6262877 (2001-07-01), Mosley
patent: 11-317490 (1999-11-01), None

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