Multiple task oriented processor

Details Multiple task oriented processor Multiple task oriented processor

1983-06-17

1986-05-27

Thomas, James D.

Boots, shoes, and leggings

G06F 1216, G06F 1206, G06F 1552

Patent

active

045919763

ABSTRACT:
The computer system for missile guidance comprises five parallel processors interconnected by a global bus; with each processor having its own CPU, program memory, temporary memory, and two critical variable memories, interconnected by a local bus. The program memory and critical variable memory are hard MNOS to survive nuclear radiation. Each processor has its own cycle time, synchronized by a master clock. In each processor, the cycle has three phases for intercommunication, task processing, and critical variable storage. Thus the critical variables are stored only after task processing is completed.

REFERENCES:
patent: 4044337 (1977-08-01), Hicks et al.
patent: 4164787 (1979-08-01), Aranguren
patent: 4219873 (1980-08-01), Kober et al.
patent: 4251864 (1981-02-01), Kindell et al.
patent: 4296464 (1981-10-01), Woods et al.
patent: 4412281 (1983-10-01), Works
patent: 4413327 (1983-11-01), Sabo et al.
patent: 4414624 (1983-11-01), Summer, Jr. et al.
patent: 4445198 (1984-04-01), Eckert
patent: 4462077 (1984-07-01), York

Affiliated with

Also associated with

Rating

Multiple task oriented processor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple task oriented processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple task oriented processor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1574489