Multiple synthesizer based timing signal generation scheme

Details Multiple synthesizer based timing signal generation scheme Multiple synthesizer based timing signal generation scheme

1999-05-10

2001-01-09

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000

Reexamination Certificate

active

06172937

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to electronic systems. More particularly, the invention relates to a multiple synthesizer based scheme for generating timing signals in an electronic system.
BACKGROUND OF THE INVENTION
Source synchronous data transfer schemes have been used to increase data transfer rate as compared to common clocked data transfer schemes. While common clocked data transfer schemes use a common clock signal for devices on the sending and receiving ends of a data transfer, in source synchronous data transfer schemes, the sending device provides one or more strobe signals with the data being transferred. The receiving device uses the strobe signal to sample the incoming data.
In order to maximize data transfer, the sampling point as determined by the strobe signal should be in the center of the data time period. This provides a setup margin of one-half data period and a hold margin of one-half data period. The strobe signal can be centered by the sending device or by the receiving device. What is needed is method and apparatus to center strobe signals with respect to the data signals with which the strobe signals are transferred.
SUMMARY OF THE INVENTION
Multiple synthesizer based timing signal generation scheme is described. In one embodiment a core clock signal is generated based, at least in part, on a system clock signal. A bus clock signal is generated based, at least in part, on the core clock signal. A strobe signal is generated based, at least in part on the secondary clock signal. The strobe signal corresponds to alternative transitions of the secondary clock signal and data is output on alternating secondary clock transitions on which the strobe signal does not change state.
In one embodiment, a core clock signal is generated based, at least in part, on a system clock signal. A secondary clock signal is also generated based, at least in part, on the system clock signal. A strobe signal is generated based, at least in part on the secondary clock signal. The strobe signal corresponds to alternative transitions of the secondary clock signal and data is output on alternating secondary clock transitions on which the strobe signal does not change state.


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