Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-06-05
2001-05-15
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S523000, C712S221000
Reexamination Certificate
active
06233596
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an information processing circuit, a microcomputer, and electronic equipment.
2. Description of Related Art
Demand has increased recently for a microcomputer that is capable of executing sum-of-products operation instructions rapidly. If a microcomputer can execute sum-of-products operations rapidly, it will be able to act as a digital signal processor (DSP), a dedicated image-processing IC, or a dedicated sound-processing IC, which would lower the costs of completed products and help simplify systems.
A sum-of-products operation instruction is executed by a microcomputer as described below. First of all, first sum-of-products input data has been stored in a first area in memory and second sum-of-products input data has been stored in a second area thereof. The microcomputer then uses two addresses that are specified by the contents of internal general-purpose registers to read from memory the first and second sum-of-products input data stored in these first and second areas. It then multiplies these first and second sum-of-products input data and a sum-of-products operation circuit adds the result to an internal register for the sum-of-products result (a MAC register)
However, a microcomputer that is capable of executing a sum-of-products operation instruction has the following problems:
(1) If the microcomputer is to execute the sum-of-products operations a plurality of times, the program must be written to have a sequence of the same number of sum-of-products operation instructions as the number of times that the sum-of-products operation instruction is to be repeated. Thus, if the number of times the sum-of-products operation is to be executed is increased, it is necessary to store a corresponding number of sum-of-products operation instructions, which increases the memory capacity required. One technique for solving this problem that could be considered is to write a program which executes sum-of-products operations while decrementing the number of times the sum-of-products operation is to be executed, then escapes from this loop when the number of executions reaches zero. This technique, however, increases the time required for executing each sum-of-products operation.
(2) If sum-of-products operations are executed sequentially, the execution time for one operation is limited by the time taken to read the first and second sum-of-products input data from memory.
(3) Up until now, first and second sum-of-products input data that are each of 16 bits, for example, are multiplied and the result of the multiplication is added to a 48-bit MAC register (a register for the sum-of-products result). In such a case, it is necessary to complete addition of the 48-bit data within one clock period, so this add processing becomes a critical path. Since the MAC register is only 48 bits long, it soon overflows if the sum-of-products operation is to be executed a large number of times.
SUMMARY OF THE INVENTION
The present invention was devised with the aim of solving the above described problems and has as an objective thereof the provision of an information processing circuit, microcomputer, and electronic equipment that are designed to improve the memory usage ratio of a program that uses sum-of-products operation instructions.
Another objective of this invention is to provide an information processing circuit, microcomputer, and electronic equipment that enable improvements in the speed with which sum-of-products operation instructions are executed.
A further objective of this invention is to provide an information processing circuit, microcomputer, and electronic equipment that are designed to solve the problem of the critical path of sum-of-products operations and prevent overflow during sum-of-products operations.
In order to solve the above described problems, there is provided an information processing circuit in accordance with a first aspect of this invention, comprising: a control circuit for receiving instructions that comprise a sum-of-products operation instruction, analyzing these instructions, and controlling the execution of these instructions; and a sum-of-products operation circuit for executing a sum-of-products operation under the control of the control circuit, based on the sum-of-products operation instruction; wherein the sum-of-products operation circuit executes a sum-of-products operation a number of times specified by number-of-executions information comprised within the sum-of-products operation instruction.
In accordance with this aspect of the invention, number-of-executions information for specifying the number of times the sum-of-products operation is to be executed is comprised within the sum-of-products operation instruction. The sum-of-products operation circuit executes sum-of-products operations a number of times that is specified by the number-of-executions information comprised within the sum-of-products operation instruction, under the control of the control circuit. This makes it possible to use a single instruction to execute sum-of-products operations a desired number of times. It is therefore possible to greatly reduce the memory capacity required for the sum-of-products operations and thus improve the memory usage ratio, in comparison with the technique using a sequence of the same number of sum-of-products operation instructions as the sum-of-products operations. In addition, it is not necessary to fetch a sum-of-products operation instruction each time during the execution of the sum-of-products operations, making it possible to avoid delays in the execution of the sum-of-products operation instruction.
The information processing circuit may further comprise a circuit for decrementing a number of times that the sum-of-products operation is to be executed, in synchronization with the execution of a sum-of-products operation, where this number is stored in a register comprised within the control circuit; wherein the sum-of-products operation circuit executes sum-of-products operations until the number of executions reaches a given value. This makes it unnecessary to read the number of executions from memory at each execution of the sum-of-products operation, enabling an improvement in processing speed. If an interrupt has occurred during the execution of a plurality of sum-of-products operations, this configuration also makes it possible to resume executing the sum-of-products operations after the interrupt processing, based on the number of executions stored in the register.
The sum-of-products operation instruction may comprise an operand for specifying one register from a group consisting of a register for the number of times the sum-of-products operation is to be executed, a register for first sum-of-products input data, and a register for second sum-of-products input data; and the control circuit may specify a register other than that one register, in accordance with a given rule based on the operand that specifies that one register. This makes it possible to reduce the instruction bit length and thus make the program code more compact.
The sum-of-products operation instruction may comprise an operand for specifying a register for the number of times the sum-of-products operation is to be executed, an operand for specifying a register for first sum-of-products input data, and an operand for specifying a register for second sum-of-products input data. In addition, the control circuit may comprise at least one of a dedicated register for the number of times the sum-of-products operation is to be executed, a dedicated register for first sum-of-products input data, and a dedicated register for second sum-of-products input data; and the sum-of-products operation instruction may comprise an operation code which uses that at least one dedicated register as an implicit operand.
When an interrupt request has occurred during the execution of the number of sum-of-products operations as specified by the number-of-executions information, the control circuit receives the in
Kubota Satoshi
Kudo Makoto
Miyayama Yoshiyuki
Malzahn David H.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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