Multiple-step inner lead of leadframe

Details Multiple-step inner lead of leadframe Multiple-step inner lead of leadframe

2001-04-26

2003-05-06

Lebentritt, Michael S. (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S666000, C257S668000, C257S669000, C257S686000, C257S723000, C257S724000

Reexamination Certificate

active

06559526

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a stacked-type multi-chip package, and more particularly relates to a stacked-type multi-chip package of a leadframe.
2. Description of the Prior Art
In the interest of higher performance equipment and lower cost, increased miniaturization of components and greater packaging density have been the most goals of the computer industry. The density of the IC package is primarily limited by the available area of die mounting and the total height of the IC package. An conventional method of increasing density is to stack die or chips vertically.
Referring to
FIG. 1
, a structure presented here is a conventional structure of a stacked-type multi-chip package. A chip
120
and a chip
130
are vertically stacked on a leadframe paddle
100
by using a adhesive film
150
and has a plurality of inner leads
102
around the leadframe paddle
100
. A plurality of wires
122
and a plurality of wires
132
are connecting the active surface of the chip
120
and the active surface of the chip
130
to those inner leads
102
.
U.S. Pat. No. 6,118,176 issued to ASE in 2000 discloses a structure of a stacked chip assembly, which stacks two chips. Chips are both on the same side of the leadframe die paddle. The inner-lead is step-like to use for bearing the body of stacked chips. U.S. Pat. No. 6,087,718 issued to LG Semicon in 2000 discloses a stacked-type semiconductor chip package. The major function of the inner lead is to bear the chip. U.S. Pat. No. 5,804,874 issued to Samsung in 1998 discloses a structure of a plurality of lead on chip type semiconductor chips. The major function of the inner lead is to bear the chip. U.S. Pat. No. 5,530,281 issued to VLSI in 1996 and U.S. Pat. No. 4,987,473 issued to VLSI in 1991 both disclose similar inner leads, which are in different planarity and stagger, can shorten the bonding wires and avoid wires crossing. U.S. Pat. No. 5,291,061 issued to Micron in 1994 discloses a structure of a multi-chip stacked die device. The upward inner leads in different planarity can shorten the wire bond length.
In the foregoing references, there are still many disadvantages need to overcome. For example, the design of the lead makes the process more difficult and different directions wires bonding process needs additional tooling cost and more process difficulty. Special layout on inner leadframe or on bond pad will raise the package cost and the process difficulty.
Current multi-chip stacked package of the leadframe has essentially two kinds of structures. One is stacking chips on both sides of the leadframe paddle and the active side of two chips is in contrary directions. This structure needs design a special bond pad for one chip and a reversal process. The process is complicated and not easily controlled. Furthermore, chips will be damaged easily in stacking processes and the process cost is higher. Another structure is stacking chips on one side of the leadframe paddle and active sides of chips are faced in same directions. This package can be useed standard product and they do not need special layout on chips. In the design rule of the leadframe of the stacked-type multi-chip package, the normal way is a slot leadframe combining using a special stacked structure or a stacked multiple inner leads of the leadframe. However, these structures are having many limitations and the process is complicated and difficult controlled.
SUMMARY OF THE INVENTION
The primary object of the invention is to improve the structure of the inner lead of the leadframe to reduce the difficulty of bonding and to raise the reliability of the stacked-type multi-chip package.
Another object of the invention is to provide a structure of a stacked-type multi-chip package of the leadframe which inner leads are designed as a stair-like shape.
A further object of the invention is to provide a stacked-type multi-chip package of a leadframe having stair-like inner leads to reduce the difficulty of bonding and to raise the reliability of the multi-chip stack package.
In order to achieve previous objects of the invention, a structure of a stacked-type multi-chip package of a leadframe comprises following essential elements is provided. A leadframe paddle and a plurality of upward stair-like leads are provided, wherein each of the stair-like leads has several steps. A first chip is mounted on the leadframe paddle, wherein an active surface of the first chip is opposed to the leadframe paddle. A plurality of first wires are connecting a first horizontal step of the stair-like leads to the active surface of the first chip, wherein the first horizontal step of the stair-like leads is nearest the leadframe paddle. A second chip is stacked on the first chip, wherein an active surface of the second chip is opposed to the leadframe paddle. A plurality of second wires are connecting the second horizontal step of the stair-like leads to the active surface of the second chip, wherein the second horizontal step of the stair-like leads is upward extended from the first horizontal step.


REFERENCES:
patent: 4987473 (1991-01-01), Johnson
patent: 5291061 (1994-03-01), Ball
patent: 5530281 (1996-06-01), Groover et al.
patent: 5804874 (1998-09-01), An et al.
patent: 6087718 (2000-07-01), Cho
patent: 6087722 (2000-07-01), Lee et al.
patent: 6118174 (2000-09-01), Kim
patent: 6118176 (2000-09-01), Tao et al.

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