Multiple state responsive delta-sigma converter and delay line

Details Multiple state responsive delta-sigma converter and delay line Multiple state responsive delta-sigma converter and delay line

1976-03-15

1978-07-18

Sloyan, Thomas J.

Communications: electrical

Audible indication

Percussion-type sound producer

179 1T, 325 38B, 332 11D, 340347M, H03K 1302

Patent

active

041018818

ABSTRACT:
A digital delay line for an analog signal having an improved efficiency in converting between the analog and digital signal formats. The delay line operates by converting an analog output into a representative series of binary ones and zeros which are applied through a shift register at a set clock rate. The shift register output, at a selected delay interval, is reconverted to the original analog levels. The conversions are governed by a logic network which increases the conversion efficiency to permit a lower clock rate and shorter shift register without a corresponding loss in frequency response.

REFERENCES:
patent: 3711850 (1973-01-01), Kelly
patent: 3877026 (1975-04-01), Wintz et al.
patent: 3905028 (1975-09-01), Wintz et al.
patent: 3949299 (1976-04-01), Song
patent: 3979676 (1976-09-01), Poma
Analog Devices, Inc., Analog-Digital Conversion Handbook, 6/72, pp. I-70, I-71, I-84 to I-87, II-46 to II-49.

Affiliated with

Also associated with

Rating

Multiple state responsive delta-sigma converter and delay line does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple state responsive delta-sigma converter and delay line, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple state responsive delta-sigma converter and delay line will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-342075