Static information storage and retrieval – Powering
Patent
1999-02-19
2000-06-13
Mai, Son
Static information storage and retrieval
Powering
365194, 36523003, G11C 700
Patent
active
060757418
ABSTRACT:
A complementary metal-oxide semiconductor (CMOS) integrated circuit, such as a dynamic random access memory (DRAM), is powered by supply voltage. The CMOS integrated circuit is divided into n circuit portions including a first circuit portion and a second circuit portion. Control circuitry generates a first powerup control signal. A first switch couples the supply voltage to the first circuit portion based on the first powerup control signal being active. The first powerup control signal is delayed by a selected time delay to produce a second powerup control signal. Alternatively, the second powerup control signal is generated independent of the first powerup control signal, but is active the selected time delay after the first powerup control signal is active. A second switch couples the supply voltage to the second circuit portion based on the second powerup control signal being active.
REFERENCES:
patent: 4647956 (1987-03-01), Shrivastava
patent: 5224010 (1993-06-01), Tran
patent: 5408144 (1995-04-01), Sakata et al.
patent: 5446367 (1995-08-01), Pinney
patent: 5574697 (1996-11-01), Manning
patent: 5615162 (1997-03-01), Houston
patent: 5774399 (1998-06-01), Kwon
patent: 5781490 (1998-07-01), Ma et al.
patent: 5787044 (1998-07-01), Duesman
Ma Manny K.F.
Manning Troy A.
Mai Son
Micro)n Technology, Inc.
LandOfFree
Multiple staged power up of integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiple staged power up of integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple staged power up of integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2074787