Multiple stacked-chip packaging structure

Details Multiple stacked-chip packaging structure Multiple stacked-chip packaging structure

2006-08-15

2006-08-15

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S684000, C257S685000, C438S107000, C438S108000, C438S109000

Reexamination Certificate

active

07091590

ABSTRACT:
The invention provides a multiple stacked-chip packaging structure, including: at least one lower layer chip located on a substrate, wherein a plurality of wires are electrically connected to the bonding pads on the lower layer chip and to the substrate; at least one carrier cap provided on the lower layer chip to provide an accommodating space to the bonding pads and the wires on the lower layer chip; at least one upper layer chip provided on the carrier cap, wherein a plurality of wires are electrically connected to the bonding pads on the upper layer chip and to the substrate; and finally, a Molding Compound used to wrap up the foregoing components. The advantages of the invention are that the invention is not limited by the layout patterns of bonding pads on the chip, that the needed chips can be placed on either the upper layer or the lower layer structure according to the requirement, and that the degree of coplanar can be ensured when performing wire bonding on the upper layer chip so as to facilitate the wire bonding process.

REFERENCES:
patent: 6414384 (2002-07-01), Lo et al.
patent: 2002/0125580 (2002-09-01), Wang et al.
patent: 2002/0140073 (2002-10-01), Pai et al.
patent: 2002/0171136 (2002-11-01), Hiraoka et al.
patent: 2003/0062628 (2003-04-01), Lee et al.
patent: 2003/0178715 (2003-09-01), Sturcken et al.

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