Multiple speed synchronous bus having single clock path for prov

Details Multiple speed synchronous bus having single clock path for prov Multiple speed synchronous bus having single clock path for prov

1990-04-16

1993-11-16

Harrell, Robert B.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

395325, 395550, 395775, 3408252, 364131, 364132, 3642403, 3642304, 3642703, 364DIG1, G06F 1300

Patent

active

052631729

ABSTRACT:
A computer system which includes a synchronous digital, multibit system bus having a clock path, a master speed indicator path and a slave speed indicator path, a bus control circuit which provides first and second clocks to the clock path of the bus, the second clock having a different frequency than the first clock, and a master circuit and a slave circuit connected to the system bus. The master circuit includes master speed indication circuitry which provides a master speed indicator indicating the operating speed of the master circuit to the master speed indicator path. The slave circuit includes slave speed indication circuitry which provides a slave speed indicator indicating the operating speed of the slave circuit to the slave speed indicator path. The bus controller provides the second clock when the master speed indicator and the slave speed indicator indicate that the master circuit and the slave circuit both may function at the different frequency of the second clock.

REFERENCES:
patent: 4412282 (1983-10-01), Holden
patent: 4519034 (1985-05-01), Smith et al.
patent: 4523274 (1985-06-01), Fukunaga et al.
patent: 4580213 (1986-04-01), Hulett et al.
patent: 4677433 (1987-06-01), Catlin et al.
patent: 5077686 (1991-12-01), Rubinstein
patent: 5109490 (1992-04-01), Arimilli et al.

Affiliated with

Also associated with

Rating

Multiple speed synchronous bus having single clock path for prov does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple speed synchronous bus having single clock path for prov, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple speed synchronous bus having single clock path for prov will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-29543