Multiple sources ESD protection for an epitaxy wafer substrate

Details Multiple sources ESD protection for an epitaxy wafer substrate Multiple sources ESD protection for an epitaxy wafer substrate

2000-02-04

2002-04-02

Ballato, Josie (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

06366435

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to an electrostatic discharge (ESD) protection circuit More particularly, this invention relates to a multiple sources electrostatic discharge protection circuit applicable for being used in an epitaxy wafer.
2. Description of the Related Art
In a fabrication process of an integrated circuit (IC) such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or after the chip is fabricated, the electrostatic discharge is the major cause to damage the intetrated circuit. For example, when a human being walking on a blanket, in an environment with a high relative humidity (HR), the human being may carry from hundreds to thousands of electrostatic voltages. When the relative humidity is low, more than ten thousand of electrostatic voltages may be carried. In case the carried electrostatic charges are in contact with the chip, the chip is easily damaged to malfunction. To avoid the electrostatic discharge damage, various electrostatic protection methods or apparatus are developed. A very common type of electrostatic protection is to design an on-chip electrostatic discharge protection circuit between the internal circuit and each pad.
However, as the size of the integrated circuits reduces as the increase of the integration, the breakdown voltage of the gate oxide is approaching the junction breakdown voltage of the source/drain region, or even lower. The performance of the electrostatic discharge protection circuit is thus greatly deteriorated. In addition, the internal circuit is typically designed according to the minimum design rules without a proper design to withstand a huge electrostatic discharge transient current. For example, the space between the contact window and the edge diffusion region and between the contact window and the edge of the gate is designed insufficiently large. Under a high integration, the chip is easily to be damaged by the electrostatic discharge. Therefore, the electrostatic discharge has become a major cause to damage the deep submicron integrated circuit.
FIG. 1
shows a circuit diagram of a conventional electrostatic discharge circuit. In
FIG. 1
, an electrostatic electricity entering from an I/O pad
10
can be connected to an earth line Vss to discharge via the N-type metal-oxide semiconductor (NMOS) transistor
12
. Or alternatively, the electrostatic electricity can also be discharged to a voltage source Vdd via the PMOS transistor
14
. In both manners, the internal circuit
16
can be protected.
FIG. 2
shows a cross-sectional view of a protection circuit as shown in
FIG. 1
being constructed on a P-type (P+) epitaxy wafer (epi-wafer).
When the protection circuit as shown in
FIG. 1
is constructed on the P+epi-wafer as shown in
FIG. 2
, the influence upon the PMOS
14
due the low resistance of the P+ epi-wafer
18
is smaller with the N-well
20
as an isolation from the epi-wafer
18
. For the NMOS
12
, a current to trigger a lateral NPN transistor
22
is greatly increased being affected by the low resistant P+ epi-wafer
18
. That is, it requires a larger current to turn on the lateral NPN transistor
22
. In addition, as the thickness of the epitaxial layer becomes thinner, the influence is bigger. The protection effect of the electrostatic discharge protection circuit is thus discounted. Similarly, for the N+epi-wafer, the protection performance of the PMOS is greatly deteriorated. Thus, the circuit construction has to be modified while being built up on an epi-wafer.
FIG. 3
shows a circuit diagram of a conventional electrostatic charge couple protection circuit. The electrostatic couple protection circuit
40
comprising two NMOS transistors
46
,
48
and two PMOS transistors
50
,
52
are disposed between the pad
42
and the internal circuit
44
. The NMOS transistor
46
has a source region coupled to ground (the ground voltage Vss), a gate coupled to a drain region of the NMOS transistor
48
, and a drain region coupled to the I/O pad
42
. A source region of the NMOS transistor
48
is coupled to the ground voltage Vss, while a gate of thereof is coupled to a voltage source Vdd. The PMOS transistor
50
has a source region coupled to the voltage source Vdd, a gate coupled to a drain region of the PMOS transistor
52
, and a drain region coupled to the I/O pad
42
. A source region of the PMOS transistor
52
is coupled to the voltage source Vdd, and a gate thereof is coupled to the ground voltage Vss.
Under a normal operation, since the gate of the NMOS transistor
48
and the gate of the PMOS transistor
52
are coupled to the voltage source Vdd and the ground voltage Vss, respectively, the NMOS transistor
48
and the PMOS transistor
52
are both turned on. Meanwhile, the gates of both the NMOS transistor
46
and the PMOS transistor
50
are in a non-floating state to turn off the transistors of NMOS
46
and the PMOS
50
. Therefore, under the normal operation status, there are no charge couple characteristics and leakage current paths.
However, when electrostatic discharge occurs, taking the positive stress to Vss an example, since the voltage source Vdd is in a floating state (under abnormal operation state), the NMOS transistor
48
is turned off. During a transient period, the NMOS transistor
46
is turned off, while the gate thereof is in a floating state. The positive stress input from the I/O pad
42
is coupled to the gate of the NMOS transistor
46
via the parasitic capacitor
54
between the drain region and gate of the NMOS transistor
46
. Therefore, the parasitic bipolar device of the NMOS transistor
46
is turned on in advance. The positive stress voltage from the I/O pad
42
can thus discharge to the ground voltage Vss via the NMOS transistor
46
.
However, as the parasitic diode
56
of the PMOS transistor
50
is experienced a forward bias, the positive stress voltage from the I/O pad
42
is delivered to the gate of the NMOS transistor
48
being transferring from the parasitic diode
56
to the voltage source Vdd. The NMOS transistor
48
is thus turned on to deteriorated the characteristics of charge couple. The electrostatic discharge protection effect is thus degraded. The same conditions and effects are also applied to a negative stress to Vdd.
SUMMARY OF THE INVENTION
The invention provides a multiple sources electrostatic discharge protection circuit applicable for being used on a P-type substrate of epitaxy wafer. The multiple sources electrostatic discharge protection circuit is disposed between an I/O pad and an internal circuit and comprises four NMOS transistors and two PMOS transistors. The first NMOS transistor comprises a drain region coupled to the I/O pad and a gate coupled to a first voltage source. The second NMOS transistor comprises a drain region coupled to a source region of the first NMOS transistor and a gate coupled to a second voltage source. The third NMOS transistor comprises a drain region coupled to a voltage source pad and a gate coupled to the first voltage source. The fourth NMOS transistor comprises a drain region coupled to a source region of the third NMOS transistor and a gate coupled to the second voltage source. The first PMOS comprises a source region coupled to the I/O pad, a gate coupled to a source region of the second NMOS transistor and a drain region coupled to the ground voltage. The second PMOS transistor comprises a source region coupled to the voltage source pad, a gate coupled to a source region of the fourth NMOS transistor and a drain region coupled to the I/O pad. The voltage source pad is coupled to either the first or the second voltage source.
The invention further provides a multiple source electrostatic discharge protection circuit applicable for being used on an N-type substrate of epitaxy wafer. The multiple source electrostatic discharge protection circuit is disposed between an I/O pad and an internal circuit and comprises six NMOS transistors. The first NMOS transistor comprises a gate coupled t

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