Multiple source clock encoded communications error detection cir

Details Multiple source clock encoded communications error detection cir Multiple source clock encoded communications error detection cir

1981-09-28

1983-07-05

Atkinson, Charles E.

Excavating

307269, 371 62, 375110, G06F 1100

Patent

active

043922260

ABSTRACT:
This invention relates to an error detection circuit for detecting errors in a recovered clock signal from a self-clocking digital data signal. A first flip-flop is alternately set and reset by the recovered clock signal and by a clock source of supposedly equal frequency, respectively. The output of the first flip-flop is sensed by a second flip-flop at the end of a predetermined time period, as determined by the clock source, for determining that a transition in the recovered clock source occurred within the predetermined time period. If no transition occurred within the predetermined time period, the second flip-flop outputs an error signal.

REFERENCES:
patent: 3320440 (1967-05-01), Reed
patent: 3474414 (1969-10-01), Lenz
patent: 4012697 (1977-03-01), Ballinger
patent: 4122441 (1978-10-01), Robinson et al.
patent: 4144448 (1979-03-01), Pisciotta et al.
patent: 4222009 (1980-09-01), Moulton et al.
patent: 4267595 (1981-05-01), Hernandez

Affiliated with

Also associated with

Rating

Multiple source clock encoded communications error detection cir does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple source clock encoded communications error detection cir, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple source clock encoded communications error detection cir will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1443399