Multiple sliding register stacks in a computer

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364247, 3642443, 3642458, 3642459, 3642532, 3642533, 3642545, 364280, 3642808, G06F 700

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050500678

ABSTRACT:
A register architecture for a computer in which a plurality of banks of general purpose registers are used in the register files. Each of the multiple register banks is dedicated to a different user, with one of the register banks being dedicated to servicing interrupts and another of the register banks being dedicated to the operating system of the computer in which the register architecture is incorporated. Associated with each of the register banks is a smaller register bank of status registers in which information concerning the status of the computer is stored.

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Manolis G. H. Katavenis, "Reduced Instruction Set Computer Architectures for VLSI", The MIT Press, Chapter 3.2, pp. 52-64, 1986 (originally presented as a thesis in 1983).

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