Multiple sized die

Details Multiple sized die Multiple sized die

1998-01-14

2000-03-21

Williams, Alexander Oscar

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

257 48, 257202, 257786, 257620, H01L 2710

Patent

active

060406321

ABSTRACT:
A multiple-sized integrated circuit (IC) die and a method of making a multiple-sized IC die includes forming a plurality of IC dies on a semiconductor wafer. Each IC die has multiple rows of bonding pads around its periphery. Adjacent bonding pads on separate rows of each IC die are electrically connected together so that attachment to any one of the connected bond pads yields the same result. A plurality of scribe streets separate each IC die on the wafer, with the scribe street defining the width between each IC die. Rows of bonding pads reside in the scribe street area. Different rows of bonding pads may be selectively removed from the IC die by scribing the wafer so as to include one or more of the rows of bonding pads, thereby allowing one IC die design to have multiple sizes. An IC die separated from the wafer may still be sized smaller as long as there remain at least two rows of bonding pads around the periphery.

REFERENCES:
patent: 5015600 (1991-05-01), Livermore et al.
patent: 5016080 (1991-05-01), Giannella
patent: 5285082 (1994-02-01), Axer
patent: 5721151 (1998-02-01), Padmanabhan et al.
patent: 5773854 (1998-06-01), Pasch
patent: 5801406 (1998-09-01), Lubow et al.

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