Multiple shared memory arrangement wherein multiple processors i

Details Multiple shared memory arrangement wherein multiple processors i Multiple shared memory arrangement wherein multiple processors i

1989-06-12

1992-08-04

Williams, Jr., Archie E.

Boots, shoes, and leggings

364243, 3642436, 3642455, 3642457, 364246, 3642465, 364DIG1, G06F 1202, G06F 1318, G06F 1336

Patent

active

051365006

ABSTRACT:
A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected thereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.

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